參數(shù)資料
型號: PIC16F716-I/SS
廠商: Microchip Technology
文件頁數(shù): 24/136頁
文件大小: 0K
描述: IC PIC MCU FLASH 2KX14 20SSOP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 67
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 3.5KB(2K x 14)
程序存儲器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 639 (CN2011-ZH PDF)
配用: XLT20SS-1-ND - SOCKET TRANSITION 18DIP 20SSOP
I3-DB16F716-ND - BOARD DAUGHTER ICEPIC3
AC164307-ND - MODULE SKT FOR PM3 28SSOP
AC162054-ND - HEADER INTERFACE ICD2 16F716
PIC16F716
DS41206B-page 10
2007 Microchip Technology Inc.
TABLE 2-2:
SPECIAL FUNCTION REGISTER SUMMARY BANK 1
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
80h
INDF(1)
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
81h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h
PCL(1)
Program Counter’s (PC) Least Significant Byte
0000 0000
83h
STATUS(1)
IRP(4)
RP1(4)
RP0
TO
PD
ZDC
C
0001 1xxx
84h
FSR(1)
Indirect Data Memory Address Pointer
xxxx xxxx
85h
TRISA
(7)
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
---1 1111
86h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
87h-89h
Unimplemented
8Ah
PCLATH(1,2)
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
8Bh
INTCON(1)
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
8Ch
PIE1
—ADIE
CCP1IE
TMR2IE
TMR1IE
-0-- -000
8Dh
Unimplemented
8Eh
PCON
—POR
BOR
---- --qq
8Fh-91h
Unimplemented
92h
PR2
Timer2 Period Register
1111 1111
93h-9Eh
Unimplemented
9Fh
ADCON1
PCFG2
PCFG1
PCFG0
---- -000
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, Shaded locations are unimplemented,
read as ‘0’.
Note
1:
These registers can be addressed from either bank.
2:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are
transferred to the upper byte of the program counter.
3:
Other (non Power-up) Resets include: external Reset through MCLR and the Watchdog Timer Reset.
4:
The IRP and RP1 bits are reserved. Always maintain these bits clear.
5:
On any device Reset, these pins are configured as inputs.
6:
This is the value that will be in the PORT output latch.
7:
Reserved bits, do not use.
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