參數(shù)資料
型號: PIC16F84AT-20E/SO
廠商: Microchip Technology
文件頁數(shù): 19/81頁
文件大?。?/td> 0K
描述: IC MCU CMOS 20MHZ 1K FLSH 18SOIC
標(biāo)準(zhǔn)包裝: 1,100
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 1.75KB(1K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量: 68 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
PIC16F84A
DS35007B-page 24
2001 Microchip Technology Inc.
6.3
RESET
The PIC16F84A differentiates between various kinds
of RESET:
Power-on Reset (POR)
MCLR during normal operation
MCLR during SLEEP
WDT Reset (during normal operation)
WDT Wake-up (during SLEEP)
Figure 6-4 shows a simplified block diagram of the
On-Chip RESET Circuit. The MCLR Reset path has a
noise filter to ignore small pulses. The electrical speci-
fications state the pulse width requirements for the
MCLR pin.
Some registers are not affected in any RESET condition;
their status is unknown on a POR and unchanged in any
other RESET. Most other registers are reset to a “RESET
state” on POR, MCLR or WDT Reset during normal oper-
ation and on MCLR during SLEEP. They are not affected
by a WDT Reset during SLEEP, since this RESET is
viewed as the resumption of normal operation.
Table 6-3 gives a description of RESET conditions for
the program counter (PC) and the STATUS register.
Table 6-4 gives a full description of RESET states for all
registers.
The TO and PD bits are set or cleared differently in dif-
ferent RESET situations (Section 6.7). These bits are
used in software to determine the nature of the RESET.
FIGURE 6-4:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
TABLE 6-3:
RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER
S
R
Q
External Reset
MCLR
VDD
OSC1/
WDT
Module
VDD Rise
Detect
OST/PWRT
On-Chip
RC Osc(1)
WDT
Time-out
Power-on Reset
OST
10-bit Ripple Counter
PWRT
Chip_Reset
10-bit Ripple Counter
Reset
Enable OST
Enable PWRT
SLEEP
CLKIN
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2: See Table 6-5.
Condition
Program Counter
STATUS Register
Power-on Reset
000h
0001 1xxx
MCLR during normal operation
000h
000u uuuu
MCLR during SLEEP
000h
0001 0uuu
WDT Reset (during normal operation)
000h
0000 1uuu
WDT Wake-up
PC + 1
uuu0 0uuu
Interrupt wake-up from SLEEP
PC + 1(1)
uuu1 0uuu
Legend: u = unchanged, x = unknown
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
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