參數資料
型號： PIC16F84AT-20E/SO
廠商： Microchip Technology
文件頁數： 8/81頁
文件大?。?/td> 0K
描述： IC MCU CMOS 20MHZ 1K FLSH 18SOIC
標準包裝： 1,100
系列： PIC® 16F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設備： POR，WDT
輸入/輸出數： 13
程序存儲器容量： 1.75KB（1K x 14）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量： 68 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 5.5 V
振蕩器型： 外部
工作溫度： -40°C ~ 125°C
封裝/外殼： 18-SOIC（0.295"，7.50mm 寬）
包裝： 帶卷 (TR)
PIC16F84A
DS35007B-page 14
2001 Microchip Technology Inc.
3.1
Reading the EEPROM Data
Memory
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1<0>). The data is available, in the very
next cycle, in the EEDATA register; therefore, it can be
read in the next instruction. EEDATA will hold this value
until another read or until it is written to by the user
(during a write operation).
EXAMPLE 3-1:
DATA EEPROM READ
3.2
Writing to the EEPROM Data
Memory
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte.
EXAMPLE 3-2:
DATA EEPROM WRITE
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental writes
to data EEPROM due to errant (unexpected) code exe-
cution (i.e., lost programs). The user should keep the
WREN bit clear at all times, except when updating
EEPROM. The WREN bit is not cleared by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
3.3
Write Verify
Depending on the application, good programming
practice may dictate that the value written to the Data
EEPROM should be verified (Example 3-3) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the specification limit.
Generally, the EEPROM write failure will be a bit which
was written as a ’0’, but reads back as a ’1’ (due to
leakage off the bit).
EXAMPLE 3-3:
WRITE VERIFY
TABLE 3-1:
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
BCF
STATUS, RP0
; Bank 0
MOVLW
CONFIG_ADDR
;
MOVWF
EEADR
; Address to read
BSF
STATUS, RP0
; Bank 1
BSF
EECON1, RD
; EE Read
BCF
STATUS, RP0
; Bank 0
MOVF
EEDATA, W
; W = EEDATA
BSF
STATUS, RP0
; Bank 1
BCF
INTCON, GIE
; Disable INTs.
BSF
EECON1, WREN ; Enable Write
MOVLW
55h
;
MOVWF
EECON2
; Write 55h
MOVLW
AAh
;
MOVWF
EECON2
; Write AAh
BSF
EECON1,WR
; Set WR bit
;
begin write
BSF
INTCON, GIE
; Enable INTs.
R
e
qu
ir
ed
S
e
qu
en
c
e
BCF
STATUS,RP0 ; Bank 0
:
; Any code
:
; can go here
MOVF
EEDATA,W
; Must be in Bank 0
BSF
STATUS,RP0 ; Bank 1
READ
BSF
EECON1, RD
; YES, Read the
; value written
BCF
STATUS, RP0 ; Bank 0
;
; Is the value written
; (in W reg) and
; read (in EEDATA)
; the same?
;
SUBWF EEDATA, W
;
BTFSS STATUS, Z
; Is difference 0?
GOTO
WRITE_ERR
; NO, Write error
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on
all other
RESETS
08h
EEDATA
EEPROM Data Register
xxxx xxxx
uuuu uuuu
09h
EEADR
EEPROM Address Register
xxxx xxxx
uuuu uuuu
88h
EECON1
—
EEIF
WRERR
WREN
WR
RD
---0 x000
---0 q000
89h
EECON2
EEPROM Control Register 2
---- ----
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends upon condition.
Shaded cells are not used by data EEPROM.
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PIC16F84T-04/SO 功能描述:8位微控制器 -MCU 1.75KB 68 RAM 13 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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