TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
參數(shù)資料
型號(hào): PIC16F84AT-20E/SO
廠商: Microchip Technology
文件頁數(shù): 24/81頁
文件大小: 0K
描述: IC MCU CMOS 20MHZ 1K FLSH 18SOIC
標(biāo)準(zhǔn)包裝: 1,100
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 13
程序存儲(chǔ)器容量: 1.75KB(1K x 14)
程序存儲(chǔ)器類型: 閃存
EEPROM 大小: 64 x 8
RAM 容量: 68 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
PIC16F84A
DS35007B-page 28
2001 Microchip Technology Inc.
FIGURE 6-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD):
SLOW VDD RISE TIME
6.7
Time-out Sequence and
Power-down Status Bits (TO/PD)
On power-up (Figures 6-6 through 6-9), the time-out
sequence is as follows:
1.
PWRT time-out is invoked after a POR has
expired.
2.
Then, the OST is activated.
The total time-out will vary based on oscillator configu-
ration and PWRTE configuration bit status. For exam-
ple, in RC mode with the PWRT disabled, there will be
no time-out at all.
TABLE 6-5:
TIME-OUT IN VARIOUS
SITUATIONS
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high, execution will begin immediately
(Figure 6-6). This is useful for testing purposes or to
synchronize more than one PIC16F84A device when
operating in parallel.
Table 6-6 shows the significance of the TO and PD bits.
Table 6-3 lists the RESET conditions for some special
registers, while Table 6-4 lists the RESET conditions
for all the registers.
TABLE 6-6:
STATUS BITS AND THEIR
SIGNIFICANCE
VDD
MCLR
V1
When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD
has reached its final value. In this example, the chip will reset properly if, and only if, V1
≥ VDD min.
INTERNAL POR
TPWRT
TOST
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
Oscillator
Configuration
Power-up
Wake-up
from
SLEEP
PWRT
Enabled
PWRT
Disabled
XT, HS, LP
72 ms +
1024TOSC
RC
72 ms
——
TO
PD
Condition
11
Power-on Reset
0x
Illegal, TO is set on POR
x0
Illegal, PD is set on POR
01
WDT Reset (during normal operation)
00
WDT Wake-up
11
MCLR during normal operation
10
MCLR during SLEEP or interrupt
wake-up from SLEEP
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