參數(shù)資料
型號(hào)： PIC16F872T-E/SS
廠商： Microchip Technology
文件頁數(shù)： 11/167頁
文件大?。?/td> 0K
描述： IC MCU CMOS 20MHZ 2K FLSH 28SSOP
標(biāo)準(zhǔn)包裝： 2,100
系列： PIC® 16F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 22
程序存儲(chǔ)器容量： 3.5KB（2K x 14）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 5x10b
振蕩器型： 外部
工作溫度： -40°C ~ 125°C
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
包裝： 帶卷 (TR)
108
8048C–AVR–02/12
ATtiny43U
detects the start condition and sets the USISIF Flag. The flag can generate an interrupt
if necessary.
2.
In addition, the start detector will hold the SCL line low after the master has forced a
negative edge on this line (B). This allows the slave to wake up from sleep or complete
other tasks before setting up the USI Data Register to receive the address. This is done
by clearing the start condition flag and resetting the counter.
3.
The master set the first bit to be transferred and releases the SCL line (C). The slave
samples the data and shifts it into the USI Data Register at the positive edge of the SCL
clock.
4.
After eight bits containing slave address and data direction (read or write) have been
transferred, the slave counter overflows and the SCL line is forced low (D). If the slave
is not the one the master has addressed, it releases the SCL line and waits for a new
start condition.
5.
When the slave is addressed, it holds the SDA line low during the acknowledgment
cycle before holding the SCL line low again (i.e., the USI Counter Register must be set
to 14 before releasing SCL at (D)). Depending on the R/W bit the master or slave
enables its output. If the bit is set, a master read operation is in progress (i.e., the slave
drives the SDA line) The slave can hold the SCL line low after the acknowledge (E).
6.
Multiple bytes can now be transmitted, all in same direction, until a stop condition is
given by the master (F), or a new start condition is given.
If the slave is not able to receive more data it does not acknowledge the data byte it has last
received. When the master does a read operation it must terminate the operation by forcing the
acknowledge bit low after the last byte transmitted.
14.3.5
Start Condition Detector
The start condition detector is shown in Figure 14-6. The SDA line is delayed (in the range of 50
to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled
in two-wire mode.
Figure 14-6. Start Condition Detector, Logic Diagram
The start condition detector works asynchronously and can therefore wake up the processor
from power-down sleep mode. However, the protocol used might have restrictions on the SCL
hold time. Therefore, when using this feature the oscillator start-up time (set by CKSEL fuses,
see “Clock Sources” on page 24) must also be taken into consideration. Refer to the description
of the USISIF bit on page 114 for further details.
SDA
SCL
Write( USISIF)
CLOCK
HOLD
USISIF
DQ
CLR
DQ
CLR
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PIC16F872T-I/SO 功能描述:8位微控制器 -MCU 3.5KB 128 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F872T-I/SS 功能描述:8位微控制器 -MCU 3.5KB 128 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F872T-I/SS033 制造商:Microchip Technology Inc 功能描述:
PIC16F873-04/SO 功能描述:8位微控制器 -MCU 7KB 192 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F873-04/SO 制造商:Microchip Technology Inc 功能描述:8BIT FLASH MCU SMD 16F873 SOIC28
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