參數(shù)資料
型號: PIC18F6720-I/PT
廠商: Microchip Technology
文件頁數(shù): 117/165頁
文件大?。?/td> 0K
描述: IC MCU FLASH 64KX16 EE 64TQFP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 160
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 25MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 52
程序存儲器容量: 128KB(64K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 3.75K x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
配用: MA180020-ND - MODULE PLUG-IN HPC EXPL 18F87J11
XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP
AC164319-ND - MODULE SKT MPLAB PM3 64TQFP
2004 Microchip Technology Inc.
DS39609B-page 53
PIC18F6520/8520/6620/8620/6720/8720
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented
(not a physical register)
n/a
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented
(not a physical register) – value of FSR2 offset by value in WREG
n/a
FSR2H
Indirect Data Memory Address Pointer 2 High Byte
---- 0000
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx
STATUS
—N
OV
Z
DC
C
---x xxxx
TMR0H
Timer0 Register High Byte
0000 0000
TMR0L
Timer0 Register Low Byte
xxxx xxxx
T0CON
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
1111 1111
OSCCON
—SCS
---- ---0
LVDCON
IRVST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0
--00 0101
WDTCON
—SWDTE
---- ---0
RCON
IPEN
—RI
TO
PD
POR
BOR
0--1 11qq
TMR1H
Timer1 Register High Byte
xxxx xxxx
TMR1L
Timer1 Register Low Byte
xxxx xxxx
T1CON
RD16
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
0-00 0000
TMR2
Timer2 Register
0000 0000
PR2
Timer2 Period Register
1111 1111
T2CON
T2OUTPS3 T2OUTPS2 T2OUTPS1
T2OUTPS0
TMR2ON
T2CKPS1
T2CKPS0 -000 0000
SSPBUF
SSP Receive Buffer/Transmit Register
xxxx xxxx
SSPADD
SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode.
0000 0000
SSPSTAT
SMP
CKE
D/A
PS
R/W
UA
BF
0000 0000
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
SSPCON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000
ADRESH
A/D Result Register High Byte
xxxx xxxx
ADRESL
A/D Result Register Low Byte
xxxx xxxx
ADCON0
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
--00 0000
ADCON1
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
--00 0000
ADCON2
ADFM
ADCS2
ADCS1
ADCS0
0--- -000
CCPR1H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx
CCP1CON
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
CCPR2H
Capture/Compare/PWM Register 2 High Byte
xxxx xxxx
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx
CCP2CON
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
TABLE 4-3:
REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on page:
Legend:
x
= unknown, u = unchanged, – = unimplemented, q = value depends on condition
Note 1:
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator
modes.
2:
Bit 21 of the TBLPTRU allows access to the device configuration bits.
3:
These registers are unused on PIC18F6X20 devices; always maintain these clear.
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