參數(shù)資料
型號: PIC18F6720-I/PT
廠商: Microchip Technology
文件頁數(shù): 27/165頁
文件大?。?/td> 0K
描述: IC MCU FLASH 64KX16 EE 64TQFP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 160
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 25MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 52
程序存儲器容量: 128KB(64K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 3.75K x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
配用: MA180020-ND - MODULE PLUG-IN HPC EXPL 18F87J11
XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP
AC164319-ND - MODULE SKT MPLAB PM3 64TQFP
PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 120
2004 Microchip Technology Inc.
10.7
PORTG, TRISG and LATG
Registers
PORTG is a 5-bit wide, bidirectional port. The corre-
sponding data direction register is TRISG. Setting a
TRISG bit (= 1) will make the corresponding PORTG
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISG bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATG) is also memory
mapped. Read-modify-write operations on the LATG
register, read and write the latched output value for
PORTG.
PORTG is multiplexed with both CCP and USART
functions (Table 10-13). PORTG pins have Schmitt
Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings.
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
EXAMPLE 10-7:
INITIALIZING PORTG
FIGURE 10-16:
PORTG BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
CLRF
PORTG
; Initialize PORTG by
; clearing output
; data latches
CLRF
LATG
; Alternate method
; to clear output
; data latches
MOVLW
0x04
; Value used to
; initialize data
; direction
MOVWF
TRISG
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as inputs
PORTG/Peripheral Out Select
Data Bus
WR LATG
WR TRISG
Data
Latch
TRIS Latch
RD TRISG
Q
D
Q
CK
QD
EN
Peripheral Data Out
0
1
Q
D
Q
CK
P
N
VDD
VSS
RD PORTG
Peripheral Data In
I/O pin(1)
or
WR PORTG
RD LATG
Schmitt
Trigger
Note 1:
I/O pins have diode protection to VDD and VSS.
2: Peripheral Output Enable is only active if Peripheral Select is active.
TRIS
Override
Peripheral Output
Logic
TRIS OVERRIDE
Pin
Override
Peripheral
RG0
Yes
CCP3 I/O
RG1
Yes
USART1 Async
Xmit, Sync Clock
RG2
Yes
USART1 Async
Rcv, Sync Data
Out
RG3
Yes
CCP4 I/O
RG4
Yes
CCP5 I/O
Enable(2)
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