參數(shù)資料
型號： PIC18F6720-I/PT
廠商： Microchip Technology
文件頁數(shù)： 157/165頁
文件大?。?/td> 0K
描述： IC MCU FLASH 64KX16 EE 64TQFP
產(chǎn)品培訓模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝： 160
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 25MHz
連通性： I²C，SPI，UART/USART
外圍設備： 欠壓檢測/復位，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 52
程序存儲器容量： 128KB（64K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 3.75K x 8
電壓 - 電源 (Vcc/Vdd)： 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 托盤
配用： MA180020-ND - MODULE PLUG-IN HPC EXPL 18F87J11
XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP
AC164319-ND - MODULE SKT MPLAB PM3 64TQFP
2004 Microchip Technology Inc.
DS39609B-page 89
PIC18F6520/8520/6620/8620/6720/8720
9.1
INTCON Registers
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.
REGISTER 9-1:
INTCON REGISTER
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
R/W-0
R/W-x
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
bit 7
bit 0
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN (RCON<7>) = 0:
1
= Enables all unmasked interrupts
0
= Disables all interrupts
When IPEN (RCON<7>) = 1:
1
= Enables all high priority interrupts
0
= Disables all interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN (RCON<7>) = 0:
1
= Enables all unmasked peripheral interrupts
0
= Disables all peripheral interrupts
When IPEN (RCON<7>) = 1:
1
= Enables all low priority peripheral interrupts
0
= Disables all low priority peripheral interrupts
bit 5
TMR0IE: TMR0 Overflow Interrupt Enable bit
1
= Enables the TMR0 overflow interrupt
0
= Disables the TMR0 overflow interrupt
bit 4
INT0IE: INT0 External Interrupt Enable bit
1
= Enables the INT0 external interrupt
0
= Disables the INT0 external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1
= Enables the RB port change interrupt
0
= Disables the RB port change interrupt
bit 2
TMR0IF: TMR0 Overflow Interrupt Flag bit
1
= TMR0 register has overflowed (must be cleared in software)
0
= TMR0 register did not overflow
bit 1
INT0IF: INT0 External Interrupt Flag bit
1
= The INT0 external interrupt occurred (must be cleared in software)
0
= The INT0 external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit
1
= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0
= None of the RB7:RB4 pins have changed state
Note:
A mismatch condition will continue to set this bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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