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參數資料
| 型號： | PID9q-604e |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit RISC Microprocessor(32位精簡指令集微處理器) |
| 中文描述： | 32位RISC微處理器（32位精簡指令集微處理器） |
| 文件頁數： | 10/29頁 |
| 文件大?。?/td> | 543K |
| 代理商： | PID9Q-604E |
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10
PID9q-604e Hardware Datasheet
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
IBM
1.4.2.2 Input AC Specifications
Table 7 provides the input AC timing specifications for the 604e as defined in Figure 2. These
specifications are for 250, 300, 333 and 350MHz processor core frequencies.
Figure 2 provides the input timing diagram for the 604e.
Figure 2. Input Timing Diagram
Table 7. Input AC Timing Specifications
1
Vdd = AVdd = 1.9
=
±
100 mV dc, OVdd = 3.3
±
5% V dc, GND = 0 V dc, 0
≤
T
j
≤
105 °C
Num
Characteristic
250, 300, 333, 350 MHz
Unit
Notes
Min
Max
7a
ARTRY, SHD, ABB, TS, XATS, AACK,BG, DRTRY, TA, DBG,
DBB, TEA, DBDIS, and DBWO valid to SYSCLK (input setup)
3.50
—
ns
7b
All other inputs valid to SYSCLK (input setup)
7
2.50
—
ns
2
8
SYSCLK to all inputs invalid (input hold)
–0.5
—
ns
9
Mode select input valid to HRESET (input setup for DRTRY)
8 * t
sysclk
—
ns
3, 4, 5,
6
10
HRESET to mode select input invalid (input hold for DRTRY)
–0.5
—
ns
3, 4, 5,
6
Notes:
1. Input specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 0.9 V of
the rising edge of the input SYSCLK. Input and output timings are measured at the pin (see Figure 2).
2. All other input signals include the following signals—all inputs except ARTRY, SHD, ABB, TS, XATS, AACK,
BG, DRTRY, TA, DBG, DBB, DBWO, DBDIS, TEA, and JTAG inputs.
3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3).
4. t
sysclk
is the period of the external clock (SYSCLK) in nanoseconds.
5. These values are guaranteed by design, and are not tested.
6. Note this is for configuration of the fast-L2 mode and the no-DRTRY mode.
7. Setup time is extended by 0.5 ns for these signals when Hysteresis On mode is enabled.
VM
SYSCLK
ALL INPUTS
VM = Midpoint Voltage (0.9 V)
7
8
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