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參數(shù)資料
| 型號： | PID9q-604e |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit RISC Microprocessor(32位精簡指令集微處理器) |
| 中文描述： | 32位RISC微處理器（32位精簡指令集微處理器） |
| 文件頁數(shù)： | 25/29頁 |
| 文件大?。?/td> | 543K |
| 代理商： | PID9Q-604E |
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9/17/99 Revision 1.4
PID9q-604e Hardware Datasheet
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
25
Ultimately, the final selection of an appropriate heat sink for the 604e depends on many factors,
such as thermal performance at a given air velocity, spatial volume, mass, attachment method,
assembly, and cost.
1.8.6.1 Internal Package Conduction Resistance
For the exposed-die packaging technology, shown in Table 14, the intrinsic conduction thermal
resistance paths are as follows:
The die junction-to-case thermal resistance
The die junction-to-lead thermal resistance
Figure 13 depicts the primary heat transfer path for a package with an attached heat sink mounted
to a printed-circuit board.
Figure 13. C4 Package with Heat Sink Mounted to a Printed-Circuit Board
Heat generated on the active side (ball) of the chip is conducted through the silicon, then through
the heat sink attach material (or thermal interface material), and finally to the heat sink where it is
removed by forced-air convection.
Since the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop
in the silicon may be neglected. Thus, the heat sink attach material and the heat sink conduction/
convective thermal resistances are the dominant terms. The following section provides a thermal
management example for the 604e using one of the commercially available heat sinks.
Table 14. Package Thermal Resistance
Thermal Metric
CBGA
Junction-to-top of die thermal resistance
0.03 °C/W
Junction-to-lead (ball) thermal resistance
2.2 °C/W
External Resistance
External Resistance
Internal Resistance
(Note the internal versus external package resistance)
Radiation
Convection
Radiation
Convection
Heat Sink
Printed-Circuit Board
Thermal Interface Material
Package/Leads
Die Junction
Die/Package
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