參數(shù)資料
型號: PLS159
廠商: NXP Semiconductors N.V.
英文描述: Programmable logic sequencer 16 】 45 】 12
中文描述: 可編程序邏輯16】45】12
文件頁數(shù): 3/12頁
文件大?。?/td> 132K
代理商: PLS159
Philips Semiconductors Programmable Logic Devices
Product specification
PLS159A
Programmable logic sequencer
(16
×
45
×
12)
October 22, 1993
27
FUNCTIONAL DIAGRAM
C
a
b
S
Q
Q
C
a
a
b
b
X
CK
P
J
R
Q
K
M
(LOGIC TERMS)
(CONTROL TERMS)
P
A
R
A
P
B
D
E
A
B
F
T
31
T
0
F
C
(4)
OE
E
B
CK
P
J
R
Q
K
M
(4)
F
R
B
L
B
L
A
CLK
CK
LOGIC FUNCTION
0
1
0
0
0
1
STATE REGISTER
S
R
S
n + 1
PRESENT STATE
A
B
C
. . .
NEXT STATE
Q2
Q1
Q0
SET Q
0
: J
0
= (Q
3
Q
2
Q
1
Q
0
)
A
B
C . . .
K
0
= 0
RESET Q
1
: J
1
= 0
K
1
= (Q
3
Q
2
Q
1
Q
0
)
A
B
C . . .
HOLD Q
2
: J
2
= 0
K
2
= 0
1
0
Q3
TOGGLE Q
3
: J
3
= (Q
3
Q
2
Q
1
Q
0
)
A
B
C . . .
K
3
= (Q
3
Q
2
Q
1
Q
0
)
A
B
C . . .
NOTE:
Similar logic functions are applicable for D
and T mode flip-flops.
FLIP-FLOP TRUTH TABLE
OE
L
CK
P
R
J
K Q
F
H
Hi-Z
L
X
X
L
X
X
X
L
H
L
X
X
H
L
X
X
H
L
L
X
X
L
H
X
X
L
H
L
L
L
L
L
L
Q
Q
L
L
L
L
L
H
L
H
L
L
L
L
H
L
H
L
L
L
L
L
H
H Q
Q
H
H
L
L
L
H
L
H*
H
H
L
L
H
L
H
L*
+10V
X
X
X
L
H
L
H* *
X
X
X
H
L
H
L* *
NOTES:
1. Positive Logic:
J-K = T
+ T
+ T
2
………………
T
31
T
= C
(I0
I1
I2
)
(Q
0
Q
1
)
(B0
B1
)
2.
denotes transition from Low to High level.
3. X = Don’t care
4. * = Forced at F
n
pin for loading the J-K
flip-flop in the Input mode. The load
control term, L
must be enabled (HIGH)
and the p-terms that are connected to the
associated flip-flop must be forced LOW
(disabled) during Preload.
5. At P = R = H, Q = H. The final state of Q
depends on which is released first.
6. * * = Forced at F
n
pin to load J-K flip-flop
independent of program code (Diagnostic
mode), 3-State B outputs.
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