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參數(shù)資料
| 型號(hào)： | PLS159AN |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | Programmable logic sequencer 16 】 45 】 12 |
| 中文描述： | OT PLD, 35 ns, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-20 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 132K |
| 代理商： | PLS159AN |
Philips Semiconductors Programmable Logic Devices
Product specification
PLS159A
Programmable logic sequencer
(16
×
45
×
12)
October 22, 1993
34
“OR” ARRAY – (Q
n
= J-K Type)
Q
J
K
T
n
M = DISABLED
ACTION
HOLD
CODE
Q
J
K
T
n
M = DISABLED
ACTION
RESET
CODE
L
Q
J
K
T
n
M = DISABLED
ACTION
SET
CODE
Q
J
K
T
n
ACTION
TOGGLE
CODE
O
–
H
M = DISABLED
“OR” ARRAY – (S or B)
“EX-OR” ARRAY – (B)
T
n
STATUS
INACTIVE
CODE
T
n
STATUS
ACTIVE
1
CODE
A
T
n
S, B
T
n
POLARITY
LOW
1
CODE
L
POLARITY
HIGH
CODE
H
S
B
S
B
S, B
“OE” ARRAY – (E)
ACTION
DISABLE
CODE
ACTION
ENABLE
4
CODE
ACTION
CONTROL
CODE
ACTION
IDLE
1, 4
CODE
O
–
A
E
n
OE
E
n
OE
E
n
OE
E
n
OE
NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates.
2. Any gate (T, F
, L, P, R, D)
will be unconditionally inhibited if both of the I, B, or Q links are left intact.
3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates T
, F
.
4. E
= O and E
=
are logically equivalent states, since both cause F
outputs to be unconditionally enabled.
5. These states are not allowed for control gates (L, P, R, D)
n
due to their lack of “OR” array links.
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