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參數(shù)資料
| 型號(hào)： | PLS159AN |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | Programmable logic sequencer 16 】 45 】 12 |
| 中文描述： | OT PLD, 35 ns, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-20 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 132K |
| 代理商： | PLS159AN |
Philips Semiconductors Programmable Logic Devices
Product specification
PLS159A
Programmable logic sequencer
(16
×
45
×
12)
October 22, 1993
35
PROGRAM TABLE
J/K
J/K or D
(controlled)
A
HIGH
LOW
H
L
0
1
2
3
0
1
2
3
4
5
6
7
(OR)
Q(N)
B(O)
POLARITY
E
A
E
B
F/F MODE
0
1
2
3
4
5
6
7
0
1
2
3
0
1
2
3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
T
E
R
M
F
C
P
B
R
B
L
B
C
AND
I
B(I)
Q(P)
D3
D2
D1
D0
PIN
5
4
3
2
9
8
7
6
19 18
17
16 15 14
13
12
C
P
P
T
P
R
D
T
C
C
D
C
AND
OR
CONTROL
NOTES
1. The device is shipped with all links intact. Thus a back-
ground of entries corresponding to states of virgin links
exists in the table, shown BLANK for clarity.
2. Program unused C, I, B, and Q bits in the AND array as (–).
Program unused Q, B, P, and R bits in the OR array as (–) or
(A), as applicable.
3. Unused Terms can be left blank.
4. Q (P) and Q (N) are respectively the present and next states
of flip-flops Q.
INACTIVE
I, B, Q
I, B, Q
DON’T CARE
O
H
L
–
INACTIVE
GENERATE
PROPAGATE
TRANSPARENT
O
A
–
I, B(I),
Q(P)
C
ACTIVE
INACTIVE
A
P, R, B(O)
(Q = D)
TOGGLE
SET
RESET
HOLD
O
H
L
–
(Q = J/K)
IDLE
CONTROL
ENABLE
DISABLE
O
A
–
E
A, B
(POL)
F/F
MODE
L
A
R
A
P
A
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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