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參數(shù)資料
| 型號(hào)： | PLSI1032-80LT |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High-Density Programmable Logic |
| 中文描述： | EE PLD, 20 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 256K |
| 代理商： | PLSI1032-80LT |
Specifications
ispLSI and pLSI 1032
13
1996 ISP Encyclopedia
Pin Description
Input – Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.
Input – This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
Input – This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
Input/Output – This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
Input – This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
These pins are not used.
Description
TQFP Pin Numbers
17,
18,
21,
22,
29,
30,
33,
34,
40,
41,
44,
45,
48,
53,
56,
57,
67,
68,
71,
72,
79,
80,
83,
84,
90,
91,
94,
95,
98,
3,
6,
7,
66,
87,
Name
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
IN 4 - IN 7
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
19,
23,
31,
35,
42,
46,
54,
58,
69,
73,
81,
85,
92,
96,
4,
8,
89,
20,
28,
32,
36,
43,
47,
55,
59,
70,
78,
82,
86,
93,
97,
5,
9
10
Dedicated input pins to the device.
ispEN*/NC
14
SDI*/IN 0
16
MODE*/IN 1
37
SDO*/IN 2
39
SCLK*/IN 3
60
NC
1,
26,
51,
76,
2,
27,
52,
77,
24,
49,
74,
99,
25,
50,
75
100
Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
Ground (GND)
V
CC
RESET
15
Y0
11
Y1
65
Y2
62
Y3
61
GND
V
CC
13,
12,
38,
64
63,
88
Table 2- 0002B-32-isp
* For ispLSI 1032 Only
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