參數(shù)資料
型號: PLV16V8
廠商: Lattice Semiconductor Corporation
英文描述: Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic
中文描述: 低電壓,零功率20引腳電子工程的CMOS通用可編程陣列邏輯
文件頁數(shù): 1/22頁
文件大小: 425K
代理商: PLV16V8
FINAL
Publication#
17713
Amendment/
0
Rev:
E
Issue Date:
November 1998
COM’L:-10
IND:-20
PALLV16V8-10 and PALLV16V8Z-20
Low Voltage, Zero Power 20-Pin EE CMOS
Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
N
Low-voltage operation, 3.3 V JEDEC compatible
— V
CC
= +3.0 V to +3.6 V
N
Pin and function compatible with all 20-pin PAL
devices
N
Electrically-erasable CMOS technology provides reconfigurable logic and full testability
N
Direct plug-in replacement for the PAL16R8 series
N
Designed to interface with both 3.3-V and 5-V logic
N
Outputs programmable as registered or combinatorial in any combination
N
Programmable output polarity
N
Programmable enable/disable control
N
Preloadable output registers for testability
N
Automatic register reset on power up
N
Cost-effective 20-pin plastic DIP PLCC, and SOIC packages
N
Extensive third-party software and programmer support
N
Fully tested for 100% programming and functional yields and high reliability
GENERAL DESCRIPTION
The PALLV16V8 is an advanced PAL
CMOS technology. It is functionally compatible with all 20-pin GAL devices. The macrocells
provide a universal device architecture. The PALLV16V8 will directly replace the PAL16R8, with the
exception of the PAL16C1.
device built with low-voltage, high-speed, electrically-erasable
The PALLV16V8Z provides zero standby power and high speed. At 30-
current, the PALLV16V8Z allows battery powered operation for an extended period.
μ
A maximum standby
The PALLV16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can
always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through floating-gate cells
in the AND logic array that can be erased electrically.
The fixed OR array allows up to eight data product terms per output for logic functions. The sum
of these products feeds the output macrocell. Each macrocell can be programmed as registered or
combinatorial with an active-high or active-low output. The output configuration is determined by
two global bits and one local bit controlling four multiplexers in each macrocell.
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