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參數(shù)資料
| 型號： | PLV16V8 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic |
| 中文描述： | 低電壓，零功率20引腳電子工程的CMOS通用可編程陣列邏輯 |
| 文件頁數(shù)： | 4/22頁 |
| 文件大?。?/td> | 425K |
| 代理商： | PLV16V8 |
4
PALLV16V8-10 and PALLV16V8Z-20 Families
SG0 replaces SG1 on the feedback multiplexer. This accommodates CLK being the adjacent pin for
MC
7
and OE the adjacent pin for MC
0
.
Registered Output Configuration
The control bit settings are SG0 = 0, SG1 = 1 and SL0
configuration. All eight product terms are available as inputs to the OR gate. Data polarity is
determined by SL1
x
.
The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The feedback
path is from Q on the register. The output buffer is enabled by OE.
x
=0. There is only one registered
Combinatorial Configurations
The PALLV16V8 has three combinatorial output configurations: dedicated output in a non-
registered device, I/O in a non-registered device and I/O in a registered device.
Dedicated Output In a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0
the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the exception
of MC
3
and MC
4
. MC
3
and MC
4
do not use feedback in this mode. Because CLK and OE are not
used in a non-registered device, pins 1 and 11 are available as input signals. Pin 1 will use the
feedback path of MC
7
,
and pin 11 will use the feedback path of MC
Combinatorial I/O In a Non-Registered Device
x
=0. All eight product terms are available to
0
.
The control bit settings are SG0 = 1, SG1 = 1, and SL0
to the OR gate. The eighth product term is used to enable the output buffer. The signal at the I/O
pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used as
an input.
x
=1. Only seven product terms are available
Because CLK and
Pin 1 will use the feedback path of MC
OE
are not used in a non-registered device, pins 1 and 11 are available as inputs.
,
and pin 11 will use the feedback path of MC
7
0
.
Combinatorial I/O in a Registered Device
The control bit settings are SG0 = 0, SG1 = 1 and SL0
to the OR gate. The eighth product term is used as the output enable. The feedback signal is the
corresponding I/O signal.
x
=1. Only seven product terms are available
Dedicated Input Configuration
The control bit settings are SG0 = 1, SG1 = 0 and SL0
MC
0
and MC
7
, the feedback signal is an adjacent I/O. For MC
pins 1 and 11. These configurations are summarized in Table 1 and illustrated in Figure 2.
x
=1. The output buffer is disabled. Except for
and MC
7
, the feedback signals are
0
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