參數(shù)資料
型號(hào)： PLV16V8
廠商： Lattice Semiconductor Corporation
英文描述： Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic
中文描述： 低電壓，零功率20引腳電子工程的CMOS通用可編程陣列邏輯
文件頁(yè)數(shù)： 18/22頁(yè)
文件大小： 425K
代理商： PLV16V8
18
PALLV16V8-10 and PALLV16V8Z-20 Families
ENDURANCE CHARACTERISTICS
The PALLV16V8 is manufactured using Vantis’ advanced electrically-erasable (EE) CMOS process.
This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, devices
can be erased and reprogrammed—a feature which allows 100% testing at the factory.
ROBUSTNESS FEATURES
The PALLV16V8 has some unique features that make it extremely robust, especially when operating
in high-speed design environments. Pull-up resistors on inputs and I/O pins cause unconnected
pins to default to a known state. Input clamping circuitry limits negative overshoot, eliminating the
possibility of false clocking caused by subsequent ringing. A special noise filter makes the
programming circuitry completely insensitive to any positive overshoot that has a pulse width of
less than about 100 ns.
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Symbol
Parameter
Test Conditions
Value
Unit
t
DR
Mn Pattern Data Retention Time
Max Storage Temperature
10
Years
Max Operating Temperature
20
Years
N
Max Reprogrammng Cycles
Normal Programmng Conditions
100
Cycles
17713D-15
Typical
Input
Typical Output
Preload
Circuitry
ESD
Protection
and
Clamping
Feedback
Input
V
CC
V
CC
> 50 k
V
CC
Programming
Voltage
Detection
Positive
Overshoot
Filter
Programming
Circuitry
Provides ESD
Protection and
Clamping
Programming
Pins only
> 50 k
V
CC
5-V Protection
17713D-14
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