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| 型號： | PLX9656 |
| 英文描述： | I/O Accelerator|PCI9656 Data Book Corrections |
| 中文描述： | I / O加速器| PCI9656數(shù)據(jù)手冊更正 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大?。?/td> | 162K |
| 代理商： | PLX9656 |
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12/19/2002
- 12 -
9656-SIL-DC1-P0-.96
Table 10. M Mode Endian Mapping For Byte Lane Mode 1
M Mode Local Bus Pin
Byte Lane Mode = 1
(BIGEND[4] = 1)
Little Endian
16-bit
8-bit
1-LD31
1-LD15
1-LD7
1-LD30
1-LD14
1-LD6
1-LD29
1-LD13
1-LD5
1-LD28
1-LD12
1-LD4
1-LD27
1-LD11
1-LD3
1-LD26
1-LD10
1-LD2
1-LD25
1-LD9
1-LD1
1-LD24
1-LD8
1-LD0
1-LD23
1-LD7
2-LD7
1-LD22
1-LD6
2-LD6
1-LD21
1-LD5
2-LD5
1-LD20
1-LD4
2-LD4
1-LD19
1-LD3
2-LD3
1-LD18
1-LD2
2-LD2
1-LD17
1-LD1
2-LD1
1-LD16
1-LD0
2-LD0
1-LD15
2-LD15
3-LD7
1-LD14
2-LD14
3-LD6
1-LD13
2-LD13
3-LD5
1-LD12
2-LD12
3-LD4
1-LD11
2-LD11
3-LD3
1-LD10
2-LD10
3-LD2
1-LD9
2-LD9
3-LD1
1-LD8
2-LD8
3-LD0
1-LD7
2-LD7
4-LD7
1-LD6
2-LD6
4-LD6
1-LD5
2-LD5
4-LD5
1-LD4
2-LD4
4-LD4
1-LD3
2-LD3
4-LD3
1-LD2
2-LD2
4-LD2
1-LD1
2-LD1
4-LD1
1-LD0
2-LD0
4-LD0
Big Endian
16-bit
1-LD7
1-LD6
1-LD5
1-LD4
1-LD3
1-LD2
1-LD1
1-LD0
1-LD15
1-LD14
1-LD13
1-LD12
1-LD11
1-LD10
1-LD9
1-LD8
2-LD7
2-LD6
2-LD5
2-LD4
2-LD3
2-LD2
2-LD1
2-LD0
2-LD15
2-LD14
2-LD13
2-LD12
2-LD11
2-LD10
2-LD9
2-LD8
PCI Pins
Mapped 2
nd
(64-bit Transfers
Only)
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AD39
AD40
AD41
AD42
AD43
AD44
AD45
AD46
AD47
AD48
AD48
AD50
AD51
AD52
AD53
AD54
AD55
AD56
AD57
AD58
AD59
AD60
AD61
AD62
AD63
Notes
1.
During 64-bit PCI transfers, the lower 32 bits of the PCI bus (AD[31:0]) are always mapped first.
2.
For each Local Bus Pin table entry,
n
-
m
means that row’s PCI pin maps to Local Bus pin
m
during Local Bus cycle
n
that either
results from the PCI cycle (PCI-to-Local Bus transfers) or results in the PCI cycle (Local Bus-to-PCI transfers). For example, a
Local Bus Pin of “2-LD10” for PCI Pin AD21 during 16–bit Little Endian Local Bus transfers (ref. the darkest shaded entry)
means that during a PCI-to-Local Bus transfer, the value of PCI Pin AD21 during each 32-bit PCI transfer will occur on Local
Bus pin LD10 of the second resulting 16-bit Local Bus transfer. During a Local Bus-to-PCI transfer, this means that the value of
PCI Pin AD21 will result from the value of Local Bus pin LD10 during the second 16-bit Local Bus transfer.
3.
The mappings in the table only occur during data phases. Addresses always map to/from PCI AD[31:0] as indicated in the 32-bit
Little Endian column after the address translation specified in the configuration registers is performed.
4.
Little and Big Endian Modes are selected by both register bits and pin signals, depending on the data phase type: Direct Master
Read/Write, Direct Slave Read/Write, DMA PCI-to-Local Bus / Local Bus-to-PCI, and Configuration Register Read/Write. See
the BIGEND register description in Table 11-41 and the BIGEND# pin description in Table 12-11 for details.
PCI Pins
Mapped 1
st
32-bit
32-bit
1-LD7
1-LD6
1-LD5
1-LD4
1-LD3
1-LD2
1-LD1
1-LD0
1-LD15
1-LD14
1-LD13
1-LD12
1-LD11
1-LD10
1-LD9
1-LD8
1-LD23
1-LD22
1-LD21
1-LD20
1-LD19
1-LD18
1-LD17
1-LD16
1-LD31
1-LD30
1-LD29
1-LD28
1-LD27
1-LD26
1-LD25
1-LD24
8-bit
1-LD7
1-LD6
1-LD5
1-LD4
1-LD3
1-LD2
1-LD1
1-LD0
2-LD7
2-LD6
2-LD5
2-LD4
2-LD3
2-LD2
2-LD1
2-LD0
3-LD7
3-LD6
3-LD5
3-LD4
3-LD3
3-LD2
3-LD1
3-LD0
4-LD7
4-LD6
4-LD5
4-LD4
4-LD3
4-LD2
4-LD1
4-LD0
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
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