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參數(shù)資料
| 型號： | PLX9656 |
| 英文描述： | I/O Accelerator|PCI9656 Data Book Corrections |
| 中文描述： | I / O加速器| PCI9656數(shù)據(jù)手冊更正 |
| 文件頁數(shù)： | 6/28頁 |
| 文件大小： | 162K |
| 代理商： | PLX9656 |
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12/19/2002
- 6 -
9656-SIL-DC1-P0-.96
5.
PCI Arbiter Enable/Disable
When using the PCI 9656, the configuration register bit that is used to enable or disable
the PCI 9656’s PCI Arbiter can only be written by the EEPROM or a Local Bus master. A
PCI master cannot be write this bit. This is true for both the PCI 9656AD and the PCI
9656BA. The description in the Blue Book regarding this is incorrect.
Register 11-57 of the Blue Book incorrectly states that the PCI Arbiter Enable bit (PCIARB[0]) can
be written by a PCI master. In fact, a PCI master cannot write the PCI Arbiter Enable bit.
The following shows the corrected entry of Register 11-57:
Table 3. (PCIARB; PCI:100h, LOC:1A0h) PCI Arbiter Control
Description
Bit
Read
Write
Value after
Reset
0
PCI Arbiter Enable.
Value of 0 indicates the PCI arbiter is disabled
and REQ0# and GNT0# are used by the PCI 9656 to acquire PCI
Bus use. Value of 1 indicates the PCI arbiter is enabled.
Yes
Local/
Serial
EEPROM
0
…
6.
PCI BAR’s 4 & 5 Unused
For Direct Slave data transfers, the PCI 9656 supports mapping two PCI address spaces
to the Local Bus using PCI Base Address Registers (BAR’s) 2 and 3. This is true for both
the PCI 9656AD and the PCI 9656BA. The Blue Book PCI Configuration Register table
regarding this is potentially confusing.
Table 11-2 of the Blue Book could be interpreted to indicate that the PCI 9656 supports mapping
four PCI address spaces to the Local Bus for Direct Slave data transfers. The PCI 9656 in fact
only supports mapping two PCI address spaces.
The following shows the corrected entries of Table 11-2.
Table 4. PCI Configuration Registers
To ensure software compatibility with other
versions of the PCI 9656 family and to ensure
compatibility with future enhancements, write 0 to
all unused bits.
31
…
PCI Base Address 4; unused
PCI Base Address 5; unused
…
PCI
Configuration
Register
Address
Local
Access
(Offset
from Chip
Select
Address)
0
PCI/
Local
Writeable
Serial
EEPROM
Writeable
20h
24h
20h
24h
Y
Y
N
N
7.
Big Endian/Little Endian/Byte Lane Mode
The Blue Book descriptions of Big Endian and Little Endian conversion are potentially
confusing.
PCI 9656 Big Endian and Little Endian conversion are detailed in Blue Book Sections 2.3 and 4.3.
The following tables provide further clarification by detailing precisely PCI 9656 signal mappings
between the PCI bus and the Local Bus during Big Endian and Little Endian conversion.
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