參數(shù)資料
型號(hào): PLX9656
英文描述: I/O Accelerator|PCI9656 Data Book Corrections
中文描述: I / O加速器| PCI9656數(shù)據(jù)手冊(cè)更正
文件頁(yè)數(shù): 17/28頁(yè)
文件大小: 162K
代理商: PLX9656
12/19/2002
- 17 -
9656-SIL-DC1-P0-.96
Table 15. M Mode Local Bus Input AC Timing Specifications
Signals
(Synchronous Inputs)
(V
CC
= 3.0V, T
a
= 85°C)
Blue Book
4.5 ns
4.5 ns
4.5 ns
4.5 ns
BIGEND#/WAIT#
4.5 ns
BURST#
4.5 ns
CCS#
4.5 ns
DP[0:3]
4.5 ns
DREQ[1:0]#
4.5 ns
LA[0:31]
4.5 ns
LD[0:31]
4.5 ns
MDREQ#/DMPAF/
EOT#
4.5 ns
RD/WR#
4.5 ns
TA#
4.5 ns
TEA#
4.5 ns
TS#
4.5 ns
TSIZ[0:1]#
4.5 ns
USERi/LLOCK#
4.5 ns
Input Clocks
Local Clock Input Frequency
PCI Clock Input Frequency
T
SETUP
T
HOLD
BB#
BDIP#
BG#
BI#
AD STA
4.9 ns
4.5 ns
4.4 ns
5.3 ns
4.8 ns
4.8 ns
1.7 ns
2.0 ns
4.4 ns
5.2 ns
4.9 ns
4.7 ns
5.3 ns
5.3 ns
5.2 ns
4.8 ns
5.0 ns
1.9 ns
Min
0 MHz
0 MHz
BA STA
2.7 ns
3.8 ns
2.9 ns
4.0 ns
3.8 ns
4.1 ns
2.9 ns
2.9 ns
3.3 ns
3.6 ns
3.1 ns
4.2 ns
3.5 ns
4.1 ns
4.4 ns
2.1 ns
3.6 ns
3.2 ns
Blue Book
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
AD STA
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
Max
66 MHz
66 MHz
BA STA
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
Table 16. M Mode Local Bus Output AC Timing Specifications
Signals
(Synchronous Outputs)
Blue Book
9 ns
BDIP#
BIGEND#/
WAIT#
BR#
BURST#
DACK[1:0]#
DP[0:3]
LA[0:31]
LD[0:31]
MDREQ#/DMPAF/
EOT#
RD/WR#
RETRY#
TA#
TEA#
TS#
TSIZ[0:1]#
USERo/LLOCKo#
Output T
VALID
(C
L
= 50pF, V
CC
= 3.0V, T
a
= 85°C)
AD
1
STA
9.4 ns
7.7 ns
7.6 ns
7.5 ns
7.6 ns
7.6 ns
7.9 ns
8.0 ns
7.8 ns
8.5 ns
7.6 ns
9.5 ns
9.0 ns
9.6 ns
7.6 ns
7.6 ns
7.6 ns
BB#
BA
2
STA
6.8 ns
6.4 ns
6.3 ns
6.8 ns
6.3 ns
6.3 ns
6.8 ns
6.8 ns
6.3 ns
6.6 ns
6.3 ns
6.8 ns
7.2 ns
7.5 ns
6.3 ns
6.3 ns
6.3 ns
9 ns
9 ns
9 ns
9 ns
9 ns
9 ns
9 ns
9 ns
9 ns
9 ns
9 ns
9 ns
9 ns
9 ns
9 ns
9 ns
1
On high-to-low transitions, output T
VALID
values increase/decrease by 23 ps for each increase/decrease of 1pF.
On low-to-high transitions, output T
VALID
values increase/decrease by 20 ps for each increase/decrease of 1pF.
2
On high-to-low transitions, output T
VALID
values increase/decrease by 16 ps for each increase/decrease of 1pF.
On low-to-high transitions, output T
VALID
values increase/decrease by 20 ps for each increase/decrease of 1pF.
On high-to-low transitions, the slew rate at 50 pF loading is 1.93 V/ns typical; .94 V/ns worst case.
On low-to-high transitions, the slew rate at 50 pF loading is 1.15 V/ns typical; .70 V/ns worst case.
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