參數(shù)資料
型號(hào): PM5945-UTP5
廠商: PMC-Sierra, Inc.
英文描述: ATM PHYSICAL INTERFACE APPLICATION BOARD FOR CAT-5 UTP
中文描述: ATM物理接口貓應(yīng)用板- 5雙絞線
文件頁(yè)數(shù): 17/84頁(yè)
文件大小: 1666K
代理商: PM5945-UTP5
S
TANDARD
P
RODUCT
PMC-Sierra, Inc.
PM5945 -UTP5
PMC-940202 ISSUE 2. APRIL 7, 1995
______________________________________________________________________________________________
APP_SAPI_UTP5
______________________________________________________________________________________________
13
Signal
Name
GND
GND
TxDat[0]
TxDat[1]
TxDat[2]
TxDat[3]
TxDat[4]
TxDat[5]
TxDat[6]
TxDat[7]
VCC
VCC
GND
TxPrty
Type
Power
Power
I
I
I
I
I
I
I
I
Power
Power
Power
I
PIN
1
2
3
5
9
11
4
6
10
12
Function
Ground
Ground
The S/UNI is configured for the 8 bit FIFO interface,
TxDat[7:0] corresponds to a cell byte.
TxDat[7] corresponds to bit 1, the first bit received.
TxDat[0] corresponds to bit 8, the last bit received.
7
8
13
14
+5 Volts
+5 Volts
Ground
Transmit data bus (TxDat[7:0]) odd parity. Not
Used
Transmit start of cell indication. Identifies the first
byte (word) of a cell on inputs TxDAT[7:0]
Ground
Ground
Active low signal from the PHY to ATM layer,
asserted by the PHY layer 4 cycles before it is no
longer able to accept transmit data.
Active low signal from the ATM layer to the PHY
layer, asserted by the ATM layer when it has a full
cell to transmit.
Ground
Ground
The transmit transfer/synchronization clock
provided by the ATM to the PHY layer for
synchronizing transfers on the TxDATA bus.
(nominally at 20 MHz).
Transmit Reference. Input for the purposes of
synchronization (e.g. 8 KHz frame marker or
SONET frame indicator). Not Used
TxSOC
I
15
GND
GND
TxFullB
Power
Power
O
16
17
18
TxClavB
I
19
GND
GND
TxCLK
Power
Power
I
20
21
22
TxRefB
I
23
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