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STANDARD PRODUCT
PM7323 RCMP-200
DATASHEET
PMC-960543
ISSUE 2
ROUTING CONTROL, MONITORING, & POLICING
200 MBPS
Proprietary and Confidential to PMC-Sierra, Inc.
and for its Customer’s Internal Use.
13
8
PIN DESCRIPTION (TOTAL 240)
Table 1
- Output Cell Interface Signals (24)
Pin Name
Type
Pin
No.
Feature
OFCLK
Input
126
The output FIFO clock (OFCLK) is used to read
words from the Output Cell Interface. OFCLK
must cycle at a 25 MHz or lower instantaneous
rate, but at a high enough rate to avoid FIFO
overflow. OSOC, OCA, OPRTY and ODAT[7:0]
are updated on the rising edge of OFCLK.
ORDENB is sampled using the rising edge of
OFCLK.
ORDENB
Input
119
The active low read enable (ORDENB) signal is
used to indicate transfers from the Output Cell
Interface. When ORDENB is sampled low using
the rising edge of OFCLK, a word is read from
the internal synchronous FIFO and output on bus
ODAT[7:0]. When ORDENB is sampled high
using the rising edge of OFCLK, no read is
performed and outputs ODAT[7:0], OPRTY and
OSOC are tristated if the OTSEN input is high.
ORDENB must operate in conjunction with
OFCLK to access the FIFO at a high enough
instantaneous rate as to avoid FIFO overflows.
ODAT[0]
ODAT[1]
ODAT[2]
ODAT[3]
ODAT[4]
ODAT[5]
ODAT[6]
ODAT[7]
Tristate
114
113
112
107
106
105
104
103
The output cell data (ODAT[7:0]) bus carries the
ATM cell octets that are read from the output
FIFO. If the IBUS8 input is high, only ODAT[7:0]
carries cell octets. The ODAT[7:0] bus is updated
on the rising edge of OFCLK.
When the Output Cell Interface is configured for
tristate operation using the OTSEN input,
tristating of the ODAT[7:0] output bus is
controlled by the ORDENB input.
When OTSEN is low, the ODAT[7:0] bus is low
when no cell is being transferred.