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STANDARD PRODUCT
PM7323 RCMP-200
DATASHEET
PMC-960543
ISSUE 2
ROUTING CONTROL, MONITORING, & POLICING
200 MBPS
Proprietary and Confidential to PMC-Sierra, Inc.
and for its Customer’s Internal Use.
79
An image of the VCVALID bit is at address location (0x04). It is provided so
that VCVALID may be sampled without clearing the interrupt status bits in this
register.
FULLI:
The FULLI bit becomes a logic 1 when the output buffer has been filled to its
4 cell capacity. This may indicate failure or congestion in the entity connected
to the Output Cell Interface. This bit is cleared when this register is read.
The FULLI bit may also become a logic 1 as a result of setting the FIFORST
bit of the Output Cell Configuration register (0x38). With the output FIFO
reset, it is unable to accept any cells, which is the same immediate symptom
as a full buffer.
UPFOVRI:
The UPFOVRI bit is set high when a Microprocessor Cell Interface extract
buffer overrun occurs. This bit is reset immediately after a read to this
register.
UPCAI:
The UPCAI bit indicates that a cell has been written into the Microprocessor
Cell extract buffer and is ready for processing. When logic 1, the UPCAI bit
indicates that the EXTCA bit in the Microprocessor Extract Buffer Control and
Status (0x10) register has been asserted. The UPCAI bit is cleared when this
register is read.
INSRDYI:
The INSRDYI bit indicates the Microprocessor Cell Interface insert buffer is
empty and is ready for another cell. This bit is cleared when this register is
read.
XFERI:
The XFERI bit indicates that the aggregate cell counters have been
transferred to holding registers and the contents should be read. When logic
1, the XFERI bit indicates that either the XFER or OVR bit in the Counter
Status (0x30) register has been asserted. The XFERI bit is cleared when this
register is read.