![](http://datasheet.mmic.net.cn/330000/PM7367-PI_datasheet_16444408/PM7367-PI_21.png)
DATA SHEET
PM7367 FREEDM-32P32
ISSUE 2
PMC-1991499
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE
7
Alternatively, in the receive direction, the FREEDM-32P32 supports a transparent
operating mode. For each provisioned transparent channel, the FREEDM-
32P32 directly transfers the received octets into host memory verbatim. If the
transparent channel is assigned to a channelised link, then the octets are aligned
to the received time-slots.
In the transmit direction, the PCI Host provides packets to transmit using a
transmit ready queue. For each provisioned HDLC channel, the FREEDM-
32P32 DMA's partial packets across the PCI bus and into the transmit partial
packet buffer. The partial packets are read out of the packet buffer by the
FREEDM-32P32 and frame check sequence is optionally calculated and inserted
at the end of each packet. Bit stuffing is performed before being assigned to a
particular link. The flag sequence is automatically inserted when there is no
packet data for a particular channel. Sequential packets are optionally separated
by two flags (an opening flag and a closing flag) or a single flag (combined
opening and closing flag). Zeros between flags are not shared. PCI bus latency
may cause one or more channels to underflow, in which case, the packets are
aborted, and the host is notified. For normal traffic, an abort sequence is
generated, followed by inter-frame time fill characters (flags or all-ones bytes)
until a new packet is sourced from the PCI host. No attempt is made to
automatically re-transmit an aborted packet.
Alternatively, in the transmit direction, the FREEDM-32P32 supports a
transparent operating mode. For each provisioned transparent channel, the
FREEDM-32P32 directly inserts the transmitted octets from host memory. If the
transparent channel is assigned to a channelised link, then the octets are aligned
to the transmitted time-slots. If a channel underflows due to excessive PCI bus
latency, an abort sequence is generated, followed by inter-frame time fill
characters (flags or all-ones bytes) to indicate idle channel. Data resumes
immediately when the FREEDM-32P32 receives new data from the host.
The FREEDM-32P32 is configured, controlled and monitored using the PCI bus
interface. The FREEDM-32P32 is implemented in low power CMOS technology.
It has TTL compatible inputs and outputs and is packaged in a 272 pin plastic
ball grid array (PBGA) package.