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參數(shù)資料
| 型號(hào)： | PM7367-PI |
| 廠商： | PMC-SIERRA INC |
| 元件分類(lèi)： | 數(shù)字傳輸電路 |
| 英文描述： | DIODE 1N4002 RECTIFYING |
| 中文描述： | DATACOM, FRAMER, PBGA272 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-272 |
| 文件頁(yè)數(shù)： | 81/323頁(yè) |
| 文件大?。?/td> | 2429K |
| 代理商： | PM7367-PI |
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DATA SHEET
PM7367 FREEDM-32P32
ISSUE 2
PMC-1991499
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE
67
TDRs are written to the cache one at a time as they are released by the TMAC.
The cache is then flushed to host memory when it becomes full, when a TD with
the IOC bit set high is released or when a TD is released as the result of
unprovisioning a channel. The cache controller may also flush the cache when it
contains fewer than six elements or if the pointer index is within six elements of
the end of the free queue. If the write pointer is near the end of the free queue,
the cache controller writes only to the end of the queue and does not start writing
from the top of the queue until the next time a flush is required. To do so would
require two host memory transactions and would be of no benefit.
8.7 Transmit HDLC Controller / Partial Packet Buffer
The Transmit HDLC Controller / Partial Packet Buffer block (THDL) contains a
partial packet buffer for PCI latency control and a transmit HDLC controller.
Packet data retrieved from the PCI host memory by the Transmit DMA Controller
block (TMAC) is stored in channel specific FIFOs residing in the partial packet
buffer. When the amount of data in a FIFO reaches a programmable threshold,
the HDLC controller is enabled to initiate transmission. The HDLC controller
performs flag generation, bit stuffing and, optionally, frame check sequence
(FCS) insertion. The FCS is software selectable to be CRC-CCITT or CRC-32.
The minimum packet size, excluding FCS, is two bytes. A single byte payload is
illegal. The HDLC controller delivers data to the Transmit Channel Assigner
block (TCAS) on demand. A packet in progress is aborted if an under-run
occurs. The THDL is programmable to operate in transparent mode where
packet data retrieved from the PCI host is transmitted verbatim.
8.7.1 Transmit HDLC Processor
The HDLC processor is a time-slice state machine that can process up to 32
independent channels. The state vector and provisioning information for each
channel is stored in a RAM. Whenever the TCAS requests data, the appropriate
state vector is read from the RAM, processed and finally written back to the
RAM. The HDLC state-machine can be configured to perform flag insertion, bit
stuffing and CRC generation. The HDLC processor requests data from the
partial packet processor whenever a request for channel data arrives. However,
the HDLC processor does not start transmitting a packet until the entire packet is
stored in the channel FIFO or until the FIFO free space is less than the software
programmable limit. If a channel FIFO under-runs, the HDLC processor aborts
the packet.
The configuration of the HDLC processor is accessed using indirect channel
read and write operations. When an indirect operation is performed, the
information is accessed from RAM during a null clock cycle inserted by the TCAS
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PDF描述 |
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| PM7367 | 32 link, 32 Channel Data Link Manager with PCI Interface |
| PM7375 | ATM SAR and PHY Processor for PCI Bus |
| PM7375-SC | LOCAL ATM SAR & PHYSICAL LAYER |
| PM7380 | FRAME ENGINE AND DATA LINK MANAGER 32P672 |
| PM7380-PI | FRAME ENGINE AND DATA LINK MANAGER 32P672 |
相關(guān)代理商/技術(shù)參數(shù) |
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| PM-737 | 制造商:Eclipse Tools 功能描述: |
| PM7375 | 制造商:PMC 制造商全稱(chēng):PMC 功能描述:LOCAL ATM SAR & PHYSICAL LAYER |
| PM7375-SC | 制造商:PMC Sierra from Components Direct 功能描述:PMC-SIERRA PM7375-SC COMMUNICATION MISC - Trays 制造商:PMC-Sierra 功能描述:PMC-Sierra PM7375-SC Communication Misc |
| PM7375-SGC | 制造商:PMC Sierra from Components Direct 功能描述:PM7375-SGC - Trays 制造商:PMC-Sierra 功能描述:PMC-Sierra PM7375-SGC Communication Misc |
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