
DATA SHEET
PM7367 FREEDM-32P32
ISSUE 2
PMC-1991499
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE
iii
8.4.5
FREE QUEUE CACHE..................................................46
8.5
PCI CONTROLLER......................................................................47
8.5.1
MASTER MACHINE ......................................................48
8.5.2
MASTER LOCAL BUS INTERFACE..............................50
8.5.3
TARGET MACHINE.......................................................51
8.5.4
CBI BUS INTERFACE ...................................................53
8.5.5
ERROR / BUS CONTROL.............................................53
8.6
TRANSMIT DMA CONTROLLER.................................................53
8.6.1
DATA STRUCTURES ....................................................54
8.6.2
TASK PRIORITIES........................................................66
8.6.3
DMA TRANSACTION CONTROLLER...........................66
8.6.4
READ DATA PIPELINE..................................................66
8.6.5
DESCRIPTOR INFORMATION CACHE........................66
8.6.6
FREE QUEUE CACHE..................................................66
8.7
TRANSMIT HDLC CONTROLLER / PARTIAL PACKET BUFFER67
8.7.1
TRANSMIT HDLC PROCESSOR..................................67
8.7.2
TRANSMIT PARTIAL PACKET BUFFER PROCESSOR68
8.8
TRANSMIT CHANNEL ASSIGNER .............................................70
8.8.1
LINE INTERFACE..........................................................71
8.8.2
PRIORITY ENCODER...................................................71
8.8.3
CHANNEL ASSIGNER ..................................................72
8.9
PERFORMANCE MONITOR .......................................................72
8.10 JTAG TEST ACCESS PORT INTERFACE...................................72
8.11 PCI HOST INTERFACE...............................................................72