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參數(shù)資料
| 型號(hào)： | PowerNP NPe405H |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Processor(32位嵌入式處理器) |
| 中文描述： | 32位嵌入式處理器（32位嵌入式處理器） |
| 文件頁數(shù)： | 36/64頁 |
| 文件大?。?/td> | 1050K |
| 代理商： | POWERNP NPE405H |
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Advance Information
PowerNP
TM
NPe405H Embedded Processor Data Sheet
36
Signal List
The table following table provides a summary of the number of package pins associated with each functional
interface group.
In the table “Signal Functional Description” on page 37, each external signal is listed along with a short
description of the signal function. The signals are grouped together according to their function. Some signals
are multiplexed on the same package pin (ball) so that the pin can be used for different functions. In most
cases, the signal name is shown in this table without any multiplexed signal names that may be associated
with it. In cases where multiplexed signals are in the same functional group, the names appear as a default
signal followed by secondary signals in square brackets (for example, PCIC0:3[BE0:3]). Active-low signals
such as BE0:3 are marked with an overline. Any signal that is not the primary (default) signal on a multiplexed
pin is shown in square backets.
The active signal on a multiplexed pin is controlled by programming. It is expected that in any single
application, a particular pin will always be programmed to serve the same function. The flexibility of
multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible.
In addition to multiplexing, many pins are also multi-purpose. For example, EMC0TxErr[EMC0Tx1En]
functions as an error output when the Ethernet interface operates in MII mode, or as a transmit enable output
when operating in RMII mode.
Another multi-purpose use occurs when the EBC peripheral controller address pins are used as outputs by
the NPe405H to broadcast an address to external slave devices when the NPe405H has control of the
external bus. However, when an external master gains ownership of the external bus, these same pins are
used as inputs which are driven by the external master and received by the EBC in the NPe405H. In this
example, the pins are also bidirectional, serving as both inputs and outputs.
The following table lists all of the I/O signals provided by the NPe405H. Please refer to “Signals Listed
Alphabetically” on page 15 for the pin number to which each signal is assigned.
Pin Summary
Group
No. of Pins
Nonmultiplexed Signals
259
Multiplexed Signals
79
Total Signal Pins
338
AV
DD
OV
DD
V
DD
Gnd
Thermal (and Gnd)
100
Reserved
0
Total Pins
580
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