參數(shù)資料
型號(hào)： PowerNP NPe405H
廠商： IBM Microeletronics
英文描述： 32-Bit Embedded Processor(32位嵌入式處理器)
中文描述： 32位嵌入式處理器（32位嵌入式處理器）
文件頁(yè)數(shù)： 51/64頁(yè)
文件大?。?/td> 1050K
代理商： POWERNP NPE405H
Advance Information
PowerNP
TM
NPe405H Embedded Processor Data Sheet
51
Peripheral Interface Clock Timings
Parameter
Min
Max
Units
PCIClk input frequency (asynchronous mode)
Note 2
66
MHz
PCIClk period (asynchronous mode)
15
Note 2
ns
PCI Clock frequency (synchronous mode)
25
33
MHz
PCI Clock period (synchronous mode - Note 3)
30
40
ns
PCIClk input high time
40% of nominal period
60% of nominal period
ns
PCIClk input low time
40% of nominal period
60% of nominal period
ns
EMC0MDClk output frequency
–
2.5
MHz
EMC0MDClk period
400
–
ns
EMC0MDClk output high time
160
–
ns
EMC0MDClk output low time
160
–
ns
PHY0TxClk input frequency
2.5
25
MHz
PHY0TxClk period
40
400
ns
PHY0TxClk input high time
35% of nominal period
–
ns
PHY0TxClk input low time
35% of nominal period
–
ns
PHY0RxClk input frequency
2.5
25
MHz
PHY0RxClk period
40
400
ns
PHY0RxClk input high time
35% of nominal period
–
ns
PHY0RxClk input low time
35% of nominal period
–
ns
PerClk output frequency–200MHz (for external master or synchronous
slaves)
–
50
MHz
PerClk period–200MHz
20
–
ns
PerClk output frequency–266MHz (for external master or synchronous
slaves)
–
66
PerClk period–266MHz
15
–
PerClk output high time
50% of nominal period
66% of nominal period
ns
PerClk output low time
33% of nominal period
50% of nominal period
ns
UARTSerClk input frequency
(Note 1)
–
1000/(2T
OPB
+2ns)
MHz
UARTSerClk period
2T
OPB
+2
T
OPB
+1
T
OPB
+1
–
–
ns
UARTSerClk input high time
–
ns
UARTSerClk input low time
–
ns
TmrClk input frequency–200MHz
50
MHz
TmrClk period–200MHz
20
–
ns
TmrClk input frequency–266MHz
–
66
TmrClk period–266MHz
15
–
TmrClk input high time
40% of nominal period
60% of nominal period
ns
TmrClk input low time
40% of nominal period
60% of nominal period
ns
Notes:
1. T
OPB
is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB
clock frequency is 50 MHz for 200MHz parts and 66MHz.for 266MHz parts.
2. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the NPe405H User’s Manual for more
information.
3. In synchronous PCI mode the PCI clock is derived from SysClk and the PCIClk input pin is unused.
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