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參數(shù)資料
| 型號： | PowerNP NPe405H |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Processor(32位嵌入式處理器) |
| 中文描述： | 32位嵌入式處理器（32位嵌入式處理器） |
| 文件頁數(shù)： | 39/64頁 |
| 文件大小： | 1050K |
| 代理商： | POWERNP NPE405H |
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Advance Information
PowerNP
TM
NPe405H Embedded Processor Data Sheet
39
EMC0TxD0[EMC0Tx0D0][EMC0Tx0D]
EMC0TxD1[EMC0Tx0D1][EMC0Tx1D]
EMC0TxD2[EMC0Tx1D0][EMC0Tx2D]
EMC0TxD3[EMC0Tx1D1][EMC0Tx3D]
Transmit Data. A nibble wide data bus towards the net.
The data is synchronous with PHY0TxClk
(MII 0[RMII 0 and 1][SMII 0, 1, 2, and 3]).
O
3.3V LVTTL
[EMC1TxD0][EMC1Tx2D0]
[EMC1TxD1][EMC1Tx2D1]
[EMC1TxD2][EMC1Tx3D0]
[EMC1TxD3][EMC1Tx3D1]
RMII Transmit Data (MII 1[RMII 0 and 1]).
O
5V tolerant
3.3V LVTTL
EMC0TxEn[EMC0Tx0En][EMC0Sync]
Transmit Enable. This signal is driven by EMAC2 to the
PHY. Data is valid during the active state of this signal.
Deassertion of this signal indicates end of frame
transmission. This signal is synchronous with PHYTxClk
(MII 0[RMII 0]).
or
SMII Sync.
O
3.3V LVTTL
EMC0TxErr[EMC0Tx1En]
Transmit Error. This signal is generated by the Ethernet
controller, is connected to the PHY and is synchronous
with the PHY0TxClk. It informs the PHY that an error was
detected (MII 0).
or
Transmit Enable [RMII 1].
O
5V tolerant
3.3V LVTTL
[EMC1TxEn][EMC1Tx2En]
Transmit Enable ([MII 1][RMII 2]).
O
5V tolerant
3.3V LVTTL
[EMC1TxErr][EMC1Tx3En]
Transmit Error. This signal is generated by the Ethernet
controller, is connected to the PHY and is synchronous
with the PHY1TxClk. It informs the PHY that an error was
detected ([MII 1]).
or
Transmit Enable [RMII 3].
O
5V tolerant
3.3V LVTTL
PHY0Col[PHY0Rx1Er]l
Collision [receive error] signal from the PHY. This is an
asynchronous signal (MII 0).
or
Receive Error ([RMII 1]).
I
5V tolerant
3.3V LVTTL
PHY0CrS[PHY0CrS0DV]
Carrier Sense signal from the PHY. This is an
asynchronous signal (MII 0).
or
Carrier sense data valid ([RMII 0]).
I
5V tolerant
3.3V LVTTL
1, 5
PHY0RxClk
Receiver medium clock. This signal is generated by the
PHY (MII 0).
I
5V tolerant
3.3V LVTTL
1, 4
PHY0RxD0[PHY0Rx0D0][PHY0Rx0D]
PHY0RxD1[PHY0Rx0D1][PHY0Rx1D]
PHY0RxD2[PHY0Rx1D0][PHY0Rx2D]
PHY0RxD3[PHY0Rx1D1][PHY0Rx3D]
Received Data. This is a nibble wide bus from the PHY.
The data is synchronous with PHY0RxClk
(MII 0[RMII 0 and 1][SMII 0, 1, 2, and 3]).
I
5V tolerant
3.3V LVTTL
1, 4
[PHY1RxD0][PHY1Rx2D0]
[PHY1RxD1][PHY1Rx2D1]
[PHY1RxD2][PHY1Rx3D0]
[PHY1RxD3][PHY1Rx3D1]
Receive Data (MII 1[RMII 0 and 1]).
I
5V tolerant
3.3V LVTTL
Signal Functional Description
(Part 3 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k
to 5V
)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
Signal Name
Description
I/O
Type
Notes
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