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參數(shù)資料
| 型號： | PowerNP NPe405H |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Processor(32位嵌入式處理器) |
| 中文描述： | 32位嵌入式處理器（32位嵌入式處理器） |
| 文件頁數(shù)： | 43/64頁 |
| 文件大?。?/td> | 1050K |
| 代理商： | POWERNP NPE405H |
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Advance Information
PowerNP
TM
NPe405H Embedded Processor Data Sheet
43
External Master Peripheral Interface
ExtReset
Peripheral Reset. Used by an external master and
synchronous peripheral slaves.
O
5V tolerant
3.3V LVTTL
HoldReq
Hold Request. Used by an external master to request
ownership of the peripheral bus.
I
5V tolerant
3.3V LVTTL
1, 5
HoldAck
Hold Acknowledge. Used by the NPe405H to transfer
ownership of peripheral bus to an external master.
O
5V tolerant
3.3V LVTTL
ExtReq
External Request. Used by an external master to indicate it
is prepared to transfer data.
I
5V tolerant
3.3V LVTTL
1, 4
ExtAck
Exteranl Acknowledgement. Used by the NPe405H to
indicate that a data transfer occurred.
O
5V tolerant
3.3V LVTTL
HoldPri
Hold Primary. Used by an external master to indicate the
priority of a given transfer (0 = high, 1 = low).
I
5V tolerant
3.3V LVTTL
1, 4
BusReq
Bus Request. Used when the NPe405H needs to regain
control of peripheral interface from an external Master.
O
5V tolerant
3.3V LVTTL
Internal Peripheral Interface
UARTSerClk
Serial Clock used to provide an alternative clock to the
internally generated serial clock. Used in cases where the
allowable internally generated baud rates are not
satisfactory. This input can be individually connected to
either or both UART0 and UART1.
I
5V tolerant
3.3V LVTTL
1, 4
UART0_Rx
UART0 Receive data.
I
5V tolerant
3.3V LVTTL
1, 4
UART0_Tx
UART0 Transmit data.
O
5V tolerant
3.3V LVTTL
[UART0_DCD]
UART0 Data Carrier Detect.
I
5V tolerant
3.3V LVTTL
1, 4
[UART0_DSR]
UART0 Data Set Ready.
I
5V tolerant
3.3V LVTTL
1, 4
[UART0_CTS]
UART0 Clear To Send.
I
5V tolerant
3.3V LVTTL
1, 4
[UART0_DTR]
UART0 Data Terminal Ready.
O
5V tolerant
3.3V LVTTL
[UART0_RTS]
UART0 Request To Send.
O
5V tolerant
3.3V LVTTL
[UART0_RI]
UART0 Ring Indicator.
I
5V tolerant
3.3V LVTTL r
1, 4
Signal Functional Description
(Part 7 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k
to 5V
)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
Signal Name
Description
I/O
Type
Notes
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