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參數(shù)資料
| 型號： | PowerPC 405GP |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC Embedded Controllers(32位RISC結(jié)構(gòu)嵌入式控制器) |
| 中文描述： | 32位RISC嵌入式控制器（32位的RISC結(jié)構(gòu)嵌入式控制器） |
| 文件頁數(shù)： | 10/58頁 |
| 文件大?。?/td> | 878K |
| 代理商： | POWERPC 405GP |
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PowerPC 405GP Embedded Processor Data Sheet
10
- Mixed ECC/non-ECC banks
- Bypass mode
External Peripheral Bus Controller (EBC)
Up to eight ROM, EPROM, SRAM, Flash, and Slave Peripheral I/O banks supported
Up to 66 MHz operation
Burst and non-burst devices
8-, 16-, 32-bit byte-addressable data bus width support
Latch data on Ready, Synchronous or Asynchronous
Programmable 2K clock time-out counter with disable for Ready
Programmable access timing per device
- 256 Wait States for non-burst
- 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses
- Programmable CSon, CSoff relative to address
- Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
Programmable address mapping
Peripheral Device pacing with external “Ready”
External master interface
- Write posting from external master
- Read prefetching on PLB for external master reads
- Bursting capable from external master
- Allows external master access to all non-EBC PLB slaves
- External master can control EBC slaves for own access and control
DMA Controller
Supports the following transfers:
- Memory-to-memory transfers
- Buffered peripheral to memory transfers
- Buffered memory to peripheral transfers
Four channels
Scatter/Gather capability for programming multiple DMA operations
8-, 16-, 32-bit peripheral support (OPB and external)
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