參數(shù)資料
型號(hào): PowerPC 405GP
廠商: IBM Microeletronics
英文描述: 32-bit RISC Embedded Controllers(32位RISC結(jié)構(gòu)嵌入式控制器)
中文描述: 32位RISC嵌入式控制器(32位的RISC結(jié)構(gòu)嵌入式控制器)
文件頁(yè)數(shù): 33/58頁(yè)
文件大小: 878K
代理商: POWERPC 405GP
PowerPC 405GP Embedded Processor Data Sheet
33
Signal Functional Description
(Part 1 of 12)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k
to 5V
)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
PCI Interface
PCIAD31
PCIAD30
PCIAD29
PCIAD28
PCIAD27
PCIAD26
PCIAD25
PCIAD24
PCIAD23
PCIAD22
PCIAD21
PCIAD20
PCIAD19
PCIAD18
PCIAD17
PCIAD16
PCIAD15
PCIAD14
PCIAD13
PCIAD12
PCIAD11
PCIAD10
PCIAD9
PCIAD8
PCIAD7
PCIAD6
PCIAD5
PCIAD4
PCIAD3
PCIAD2
PCIAD1
PCIAD0
PCI Address/Data Bus. Multiplexed address and data bus
I/O
5V tolerant
3.3V PCI
4
PCIC0[BE3]
PCIC1[BE2]
PCIC2[BE1]
PCIC3[BE0]
PCI C (bus command)
or
Byte enable
I/O
5V tolerant
3.3V PCI
4
PCIParity
PCI parity. Parity is even across PCIAD0:31 and PCIC0:3[BE0:3].
PCIParity is valid one cycle after either an address or data phase.
The PCI device that drove PCIAD0:31 is responsible for driving
PCIParity on the next PCI bus clock.
I/O
5V tolerant
3.3V PCI
4
PCIFrame
PCIFrame is driven by the current PCI bus master to indicate
beginning and duration of a PCI access.
I/O
5V tolerant
3.3V PCI
4
PCIIRDY
PCIIRDY is driven by the current PCI bus master. Assertion of
PCIIRDY indicates that the PCI initiator is ready to transfer data.
I/O
5V tolerant
3.3V PCI
4
PCITRDY
The target of the current PCI transaction drives PCITRDY.
Assertion of PCITRDY indicates that the PCI target is ready to
transfer data.
I/O
5V tolerant
3.3V PCI
4
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