參數(shù)資料
型號(hào)： PowerPC 405GP
廠商： IBM Microeletronics
英文描述： 32-bit RISC Embedded Controllers(32位RISC結(jié)構(gòu)嵌入式控制器)
中文描述： 32位RISC嵌入式控制器（32位的RISC結(jié)構(gòu)嵌入式控制器）
文件頁(yè)數(shù)： 35/58頁(yè)
文件大?。?/td> 878K
代理商： POWERPC 405GP
PowerPC 405GP Embedded Processor Data Sheet
35
Ethernet Interface
PHYRxD3
PHYRxD2
PHYRxD1
PHYRxD0
Received data. This is a nibble wide bus from the PHY. The data
is synchronous with the PHYRxClk.
I
5V tolerant
3.3V Rcvr
1, 4
EMCTxD3
EMCTxD2
EMCTxD1
EMCTxD0
Transmit data. A nibble wide data bus towards the net. The data
is synchronous to the PHYTxClk.
O
5V tolerant
3.3V LVTTL
6
PHYRxErr
Receive Error. This signal comes from the PHY and is
synchronous to the PHYRxClk.
I
5V tolerant
3.3V LVTTL
Rcvr
1, 5
PHYRxClk
Receiver Medium clock. This signal is generated by the PHY.
I
5V tolerant
3.3V LVTTL
Rcvr
1, 4
PHYRxDV
Receive Data Valid. Data on the Data Bus is valid when this
signal is activated. Deassertion of this signal indicates end of the
frame reception.
I
5V tolerant
3.3V LVTTL
Rcvr
1, 5
PHYCrS
Carrier Sense signal from the PHY. This is an asynchronous
signal.
I
5V tolerant
3.3V LVTTL
Rcvr
1, 5
EMCTxErr
Transmit Error. This signal is generated by the Ethernet
controller, is connected to the PHY and is synchronous with the
PHYTxClk. It informs the PHY that an error was detected.
O
5V tolerant
3.3V LVTTL
6
EMCTxEn
Transmit data Enabled. This signal is driven by EMAC2 to the
PHY. Data is valid during the active state of this signal.
Deassertion of this signal indicates end of frame transmission.
This signal is synchronous to the PHYTxClk.
O
5V tolerant
3.3V LVTTL
6
PHYTxClk
This clock comes from the PHY and is the Medium Transmit
clock.
I
5V tolerant
3V LVTTL
Rcvr
1, 4
PHYCol
Collision signal from the PHY. This is an asynchronous signal.
I
5V tolerant
3.3V LVTTL
Rcvr
1, 5
EMCMDClk
Management Data Clock. The MDClk is sourced to the PHY. This
clock has a period of 400ns, adjustable via
EMAC0_STACR[OPBC]. Management information is transferred
synchronously with respect to this clock.
O
5V tolerant
3.3V LVTTL
EMCMDIO[PHYMDIO]
Management Data Input/Output is a bidirectional signal between
the Ethernet controller and the PHY. It is used to transfer control
and status information.
I/O
5V tolerant
3.3V LVTTL
1, 4
Signal Functional Description
(Part 3 of 12)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k
to 5V
)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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