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參數(shù)資料
| 型號： | PPC440GRx-NpAfffTs |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440GRx Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 440GRx |
| 文件頁數(shù)： | 12/88頁 |
| 文件大?。?/td> | 603K |
| 代理商： | PPC440GRX-NPAFFFTS |
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440GRx – PPC440GRx Embedded Processor
Preliminary Data Sheet
12
AMCC Proprietary
Revision 1.08 – October 15, 2007
Public key acceleration for RSA, DSA and Diffie-Hellman
True or pseudo random number generators
– Non-deterministic true random numbers
– Pseudo random numbers with lengths of 8B or 16B
– ANSI X9.17 Annex C compliant using a DES algorithm
Interrupt controller
– Fifteen programmable, maskable interrupts
– Initiate commands via an input interrupt
– Sixteen programmable interrupts indicating completion of certain operations
– All interrupts mapped to one level- or edge-sensitive programmable interrupt output
DMA controller
– Autonomous, 4-channel
– 1024-words (32 bits/word) per DMA transfer
– Scatter/gather capability with byte aligned addressing
KASUMI Algorithm (optional)
Key scheduling hardware
f8
and
f9
algorithm support
Automatic data padding mechanism for
f9
algorithm
KASUMI encryption and decryption modes
32-bit slave interface
Fully synchronous to PLB clock
PCI Controller
The PCI interface allows connection of PCI devices to the PowerPC processor and local memory. This interface is
designed to Version 2.2 of the PCI Specification and supports 32- bit PCI devices.
Reference Specifications:
PowerPC CoreConnect Bus (PLB) Specification Version 3.1
PCI Specification Version 2.2
PCI Bus Power Management Interface Specification Version 1.1
Features include:
PCI 2.2
– Frequency to 66MHz
– 32-bit bus
PCI Host Bus Bridge or an Adapter Device's PCI interface
Internal PCI arbitration function, supporting up to six external devices, that can be disabled for use with an
external arbiter
Support for Message Signaled Interrupts
Simple message passing capability
Asynchronous to the PLB
PCI Power Management 1.1
PCI register set addressable both from on-chip processor and PCI device sides
Ability to boot from PCI bus memory
Error tracking/status
Supports initiation of transfers of the following types:
– Single beat I/O reads and writes
– Single beat and burst memory reads and writes
– Single beat configuration reads and writes (type 0 and type 1)
– Single beat special cycles
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PPC440GRx-SpAfffTs | PowerPC 440GRx Embedded Processor |
| PPC440GX-3RF800CZ | Power PC 440GX Embedded Processor |
| PPC440GX-3CC533S | Power PC 440GX Embedded Processor |
| PPC440GX-3CC667S | Power PC 440GX Embedded Processor |
| PPC440GX-3CF400C | Power PC 440GX Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440GRX-NTA400E | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440GRX-NTA400EZ | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440GRX-NTA533EZ | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440GRX-NTA667EZ | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440GRX-NUA400E | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
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