參數資料
型號: PPC440GRx-NpAfffTs
廠商: Applied Micro Circuits Corp.
英文描述: PowerPC 440GRx Embedded Processor
中文描述: 嵌入式處理器的PowerPC 440GRx
文件頁數: 83/88頁
文件大小: 603K
代理商: PPC440GRX-NPAFFFTS
440GRx – PPC440GRx Embedded Processor
Revision 1.08 – October 15, 2007
Preliminary Data Sheet
AMCC Proprietary
83
The following diagram illustrates the relationship among the signals involved with a DDR write operation.
Figure 11. DDR SDRAM Write Cycle Timing
Note:
The timing data in the following tables is based on simulation runs using Einstimer.
DQS
MemData
PLB Clk
MemClkOut
Addr/Cmd
T
SK
T
SA
T
HA
T
DS
T
DS
T
SD
T
HD
T
SD
T
HD
T
SA
= Setup time for address and command signals to MemClkOut
T
HA
= Hold time for address and command signals from MemClkOut
T
SD
= Setup time for data signals (minimum time data is valid
before
rising/falling edge of DSQ)
T
HD
= Hold time for data signals (minimum time data is valid
after
rising/falling edge of DSQ)
T
SK
= Delay from falling edge of MemClkOut to rising/falling edge of signal (skew)
T
DS
= Delay from rising/falling edge of clock to the rising/falling edge of DQS
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