參數(shù)資料
型號: PS2500AIT
廠商: Electronic Theatre Controls, Inc.
元件分類: XO, clock
英文描述: Low-Power Direct Digital Modulation Frequency Synthesizer
中文描述: 低功耗直接數(shù)字調(diào)制頻率合成器
文件頁數(shù): 25/28頁
文件大小: 184K
代理商: PS2500AIT
PS2500 2.2 GHz Fractional-N Frequency Synthesizer
- 25 -
Philsar Semiconductor Inc.
146 Colonnade Road S.
Nepean, Ontario, Canada
K2E 7Y1
Tel: 613-274-0922
Fax: 613-274-0915
www.philsar.com
PMP-001-DS2 V1.2
Mux_out Pin Tri-State Enable
= 1-bit value for tri-stating the
Mux_out
pin. When this bit is 0, the
Mux_out
pin is enabled. When this bit is 1, the
Mux_out
pin is tri-stated.
Figure 12: Hex8
Modulation Control Register
(Write only)
This register is used to configure the modulation unit of the main synthesizer.
The modulation unit provides for adding or subtracting a frequency offset to the selected center frequency
at which the main synthesizer is operating. The size of the modulation data sample, controlled by the
duration of
/CS
, can be from 2 to 12 bits wide, to provide from 4 to 4096 selectable frequency offsets steps.
The modulation data magnitude offset selects the magnitude multiplier for the modulation data and can be
from 0 to 8.
Values to be loaded are:
Modulation Data Magnitude Offset
=
4-bit value indicating magnitude multiplier (m) for the modulation
data samples. Valid values range from 0 to 13, effectively providing a 2
m
multiplication of the modulation
data sample.
Modulation Data Input Select
= 1-bit value indicating the pin on which modulation data samples are
serially input when
/CS
is between 2 and 12 bits long. When this bit is 0, modulation data samples are to be
presented on the
Data
pin. When this bit is 1, modulation data samples are to be presented on the
Mod_in
pin. For more details, please refer to section “Direct Digital Modulation” on page 10.
Modulation Address Disable
= 1-bit value indicating the presence of the address as modulation data
samples are presented on either the
Mod_in
or
Data
pins. When this bit is 0, address is presented with the
modulation data samples (i.e. all transfers are 16 bits long). When this bit is 1, no address is presented with
the modulation data samples (i.e. all transfers are 2 to 12 bits long). For more details, please refer to section
“Direct Digital Modulation” on page 10.
Reserved Bits
Modulation Data Magnitude Offset
Modulation Data Input Select
Modulation Address Disable
A3
1
0
0
1
0
2
0
3
0
4
5
6
7
8
9
10
X
11
X
A0
0
A1
0
A2
0
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