參數(shù)資料
型號: PS2500AIT
廠商: Electronic Theatre Controls, Inc.
元件分類: XO, clock
英文描述: Low-Power Direct Digital Modulation Frequency Synthesizer
中文描述: 低功耗直接數(shù)字調(diào)制頻率合成器
文件頁數(shù): 9/28頁
文件大小: 184K
代理商: PS2500AIT
PS2500 2.2 GHz Fractional-N Frequency Synthesizer
- 9 -
Philsar Semiconductor Inc.
146 Colonnade Road S.
Nepean, Ontario, Canada
K2E 7Y1
Tel: 613-274-0922
Fax: 613-274-0915
www.philsar.com
PMP-001-DS2 V1.2
Integer-N Applications
The desired division ratio for the Main or Auxiliary Synthesizer is given by:
N
integer
= F
VCO_main
/ F
div_ref
where
N
integer
is an integer number from 32 and 543 for both the main and auxiliary synthesizers.
The value to be programmed in the
Main or Auxiliary Divider Register
is given by:
N
reg
= N
integer
- 32
When in integer mode, allowed values for
N
reg
are from 0 and 511 for both the main and auxiliary
synthesizers.
Note:
As with all integer-N synthesizers, the minimum step size is related to the crystal frequency and
reference frequency division ratio.
Integer-N Example
Case 1:
To achieve a desired frequency
F
VCO_aux
of 400 MHz using a crystal frequency of 16 MHz.
Since the minimum divide ratio is 32, the reference frequency must be a maximum of 12.5 MHz. Choosing
a reference frequency divide ratio of 2 provides us with a reference frequency
F
div_ref
of 8 MHz.
Therefore, using:
N
integer
= F
VCO_aux
/ F
div_ref
= 400 / 8
= 50
The value to be programmed in the
Auxiliary Divider Register
is:
N
reg
= N
integer
- 32
= 50 - 32
= 18
= 0 0001 0010 (binary)
Summarizing,
Auxiliary Divider Register = 0 0001 0010
Register Loading Order
In applications where the main synthesizer is in 18-bit mode, the
Main Dividend MSB Register
holds the 10
MSBs of the
dividend
and the
Main Dividend LSB Register
holds the
8 LSBs of the
dividend
. The order in
which the registers controlling the main synthesizer’s divide ratio are to be loaded is:
Main Divider Register
Main Dividend LSB Register
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