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參數(shù)資料
| 型號： | PS2500AIT |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | Low-Power Direct Digital Modulation Frequency Synthesizer |
| 中文描述： | 低功耗直接數(shù)字調(diào)制頻率合成器 |
| 文件頁數(shù)： | 5/28頁 |
| 文件大?。?/td> | 184K |
| 代理商： | PS2500AIT |
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PS2500 2.2 GHz Fractional-N Frequency Synthesizer
- 5 -
Philsar Semiconductor Inc.
146 Colonnade Road S.
Nepean, Ontario, Canada
K2E 7Y1
Tel: 613-274-0922
Fax: 613-274-0915
www.philsar.com
PMP-001-DS2 V1.2
Lock Detection
When programmed for lock detection, the PS2500 provides on the
LD/PS
pin, an active low pulsing open
collector output to indicate the out-of-lock condition. When locked, the
LD/PS
pin is tri-stated (high
impedance).
Power Down
The PS2500 supports a number of power-down modes through its serial interface. For more information,
see “General Synthesizer Registers” on page 22.
Operation
This section describes the operation of the PS2500. The serial interface is described first, followed by
information on how to obtain values for the divide ratio registers.
Serial Interface
The serial interface of the PS2500 consists of three pins:
Clock
,
Data
and
/CS
. Data transfers are
controlled by the
Clock
signal which synchronizes and samples the information on the two serial data lines
(
Data
and
/CS
). The bits on the
Data
pin are shifted into a temporary register on the rising edge of
Clock
.
The
/CS
(chip select) line allows individual selection of slave devices on the same bus.
The following diagram functionally depicts how a serial transfer takes place.
Figure 2: Serial Transfer Timing Diagram
A serial transfer is initiated when a microcontroller or microprocessor forces the
/CS
line to a low state.
This is immediately followed by an address/data stream being presented to the
Data
pin that coincides with
the rising edges of the clock presented on the
Clk
line. Each rising edge of the
Clk
signal shifts in one bit of
data on the
Data
line into the shift-register. At the same time, one bit of data is being shifted out for the
Mux_out
pin (if the serial bit stream is selected) at each falling edge of
Clk
. To load any of the synthesizer
registers, 16 bits of address/data have to be presented to the
Data
line with the data LSB last while
/CS
is
low. If
/CS
is low for more than 16 clock cycles, only the last address/data bits are used for loading the
synthesizer registers.
If the
/CS
line is brought to a high state before the thirteenth clock edge on
Clk
, the bit stream is assumed
to be modulation data samples. In this case, it is assumed that no address bits are present and that all the bits
in the stream should be loaded into the
modulation data register
Clock
/CS
Data
A2
A1
A0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
XXX
X
A3
Last
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PS2500AIT-ES2/2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low-Power Direct Digital Modulation Frequency Synthesizer |
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