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參數(shù)資料
| 型號(hào)： | PSB3186 |
| 英文描述： | The IRAC1150-D2 Control Board is designed to demonstrate the performance of the IR1150S control IC in a continuous conduction mode boost converter for PFC.; A IRAC1150-D2 with Standard Packaging |
| 中文描述： | 3.3伏ISDN用戶終端訪問(wèn)控制器eXtended擴(kuò)展 |
| 文件頁(yè)數(shù)： | 78/200頁(yè) |
| 文件大?。?/td> | 2959K |
| 代理商： | PSB3186 |
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
Data Sheet
78
2003-01-30
Synchronous Transfer
While looping, shifting and switching the data can be accessed by the controller between
the synchronous transfer interrupt (STI) and the status overflow interrupt (STOV).
The microcontroller access to the CDAxy registers can be synchronized by means of
four programmable synchronous transfer interrupts (STIxy)
1)
and synchronous transfer
overflow interrupts (STOVxy)
2)
in the STI register.
Depending on the DPS bit in the corresponding CDA_TSDPxy register the STIxy is
generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock after the selected timeslot
(CDA_TSDPxy.TSS). One BCL clock is equivalent to two DCL clocks.
In the following description the index xy
0
and xy
1
are used to refer to two different
interrupt pairs (STI/STOV) out of the four CDA interrupt pairs (STI10/STOV10, STI11/
STOV11, STI20/STOV20, STI21/STOV21).
An STOVxy
0
is related to its STIxy
0
and is only generated if STIxy
0
is enabled and not
acknowledged. However, if STIxy
0
is masked, the STOVxy
0
is generated for any other
STIxy
1
which is enabled and not acknowledged.
Table 10
gives some examples for that. It is assumed that an STOV interrupt is only
generated because an STI interrupt was not acknowledged before.
In example 1 only the STIxy
0
is enabled and thus STIxy
0
is only generated. If no STI is
enabled, no interrupt will be generated even if STOV is enabled (example 2).
In example 3 STIxy
0
is enabled and generated and the corresponding STOVxy
0
is
disabled. STIxy
1
is disabled but its STOVxy
1
is enabled, and therefore STOVxy
1
is
generated due to STIxy
0
. In example 4 additionally the corresponding STOVxy
0
is
enabled, so STOVxy
0
and STOVxy
1
are both generated due to STIxy
0
.
In example 5 additionally the STIxy
1
is enabled with the result that STOVxy
0
is only
generated due to STIxy
0
and STOVxy
1
is only generated due to STIxy
1
.
Compared to the previous example STOVxy
0
is disabled in example 6, so STOVxy
0
is
not generated and STOVxy
1
is only generated for STIxy
1
but not for STIxy
0
.
Compared to example 5 in example 7 a third STOVxy
2
is enabled and thus STOVxy2 is
generated additionally for both STIxy
0
and STIxy
1
.
1)
In order to enable the STI interrupts the input of the corresponding CDA register has to be enabled. This is also
valid if only a synchronous write access is wanted. The enabling of the output alone does not effect an STI
interrupt.
2)
In order to enable the STOV interrupts the output of the corresponding CDA register has to be enabled. This
is also valid if only a synchronous read access is wanted. The enabling of the input alone does not effect an
interrupt.
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