參數(shù)資料
型號(hào): PSD813F1A-90MT
廠商: 意法半導(dǎo)體
英文描述: Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
中文描述: Flash在系統(tǒng)可編程(ISP)的周邊8位MCU,5V的
文件頁數(shù): 30/110頁
文件大?。?/td> 1685K
代理商: PSD813F1A-90MT
PSD813F1
30/110
FLASH AND EEPROM MEMORY SPECIFIC FEATURES
Flash Memory and EEPROM Sector Protect
Each Flash and EEPROM sector can be separate-
ly protected against Program and Erase functions.
Sector Protection provides additional data security
because it disables all program or erase opera-
tions. This mode can be activated through the
JTAG Port or a Device Programmer.
Sector protection can be selected for each sector
using the PSDsoft Configuration program. This will
automatically protect selected sectors when the
device is programmed through the JTAG Port or a
Device Programmer. Flash and EEPROM sectors
can be unprotected to allow updating of their con-
tents using the JTAG Port or a Device Program-
mer. The microcontroller can read (but cannot
change) the sector protection bits.
Any attempt to program or erase a protected Flash
or EEPROM sector will be ignored by the device.
The Verify operation will result in a READ of the
protected data. This allows a guarantee of the re-
tention of the Protection status.
The sector protection status can be read by the
MCU through the Flash protection and PSD/EE
protection registers (CSIOP). See
Table 10.
Reset
The Reset instruction resets the internal memory
logic state machine in a few milliseconds. Reset is
an instruction of either one write operation or three
write operations (refer to
Table 8., page 20
).
Table 10. Sector Protection/Security Bit Definition
Flash Protection Register
Note: 1. Bit Definitions:
Sec<i>_Prot
1 = Flash <i> is write protected.
Sec<i>_Prot
0 = Flash <i> is not write protected.
Table 11. Sector Protection/Security Bit Definition
PSD/EE Protection Register
Note: 1. Bit Definitions:
Sec<i>_Prot
1 = EEPROM Boot Sector <i> is write protected.
Sec<i>_Prot
0 = EEPROM Boot Sector <i> is not write protected.
Security_Bit
0 = Security Bit in device has not been set.
1 = Security Bit in device has been set.
SRAM
The SRAM is a 16 Kbit (2K x 8) memory. The
SRAM is enabled when RS0
the SRAM chip se-
lect output from the DPLD
is high. RS0 can con-
tain up to two product terms, allowing flexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
to the V
STBY
pin (PC2). If you have an external
battery connected to the PSD, the contents of the
SRAM will be retained in the event of a power loss.
The contents of the SRAM will be retained so long
as the battery voltage remains at 2V or greater.
If the supply voltage falls below the battery volt-
age, an internal power switchover to the battery
occurs.
Pin PC4 can be configured as an output that indi-
cates when power is being drawn from the exter-
nal battery. This V
BATON
signal will be high with
the supply voltage falls below the battery voltage
and the battery on PC2 is supplying power to the
internal SRAM.
The chip select signal (RS0) for the SRAM, V
STBY
,
and V
BATON
are all configured using PSDsoft Ex-
press Configuration.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec7_Prot
Sec6_Prot
Sec5_Prot
Sec4_Prot
Sec3_Prot
Sec2_Prot
Sec1_Prot
Sec0_Prot
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Security_Bit
not used
not used
not used
Sec3_Prot
Sec2_Prot
Sec1_Prot
Sec0_Prot
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