參數資料
型號: PSD813F1A-90MT
廠商: 意法半導體
英文描述: Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
中文描述: Flash在系統(tǒng)可編程(ISP)的周邊8位MCU,5V的
文件頁數: 87/110頁
文件大?。?/td> 1685K
代理商: PSD813F1A-90MT
87/110
PSD813F1
Figure 46. Input Macrocell Timing (product term clock)
Table 53. Input Macrocell Timing (5V devices)
Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to t
AVLX
and t
LXAX
.
2. ZPSD versions only.
Table 54. Input Macrocell Timing (3V Devices)
Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to t
AVLX
and t
LXAX
.
2. ZPSD Versions only.
Symbol
Parameter
Conditions
-90
-12
-15
PT
Aloc
Turbo
Off
2
Unit
Min
Max
Min
Max
Min
Max
t
IS
Input Setup Time
(Note
1
)
0
0
0
ns
t
IH
Input Hold Time
(Note
1
)
20
22
26
+ 10
ns
t
INH
NIB Input High Time
(Note
1
)
12
15
18
ns
t
INL
NIB Input Low Time
(Note
1
)
12
15
18
ns
t
INO
NIB Input to Combinatorial
Delay
(Note
1
)
46
50
59
+ 2
+ 10
ns
Symbol
Parameter
Conditions
-15
-20
PT
Aloc
Turbo
Off
2
Unit
Min
Max
Min
Max
t
IS
Input Setup Time
(Note
1
)
0
0
ns
t
IH
Input Hold Time
(Note
1
)
25
30
+ 20
ns
t
INH
NIB Input High Time
(Note
1
)
13
15
ns
t
INL
NIB Input Low Time
(Note
1
)
13
15
ns
t
INO
NIB Input to Combinatorial Delay
(Note
1
)
62
70
+ 4
+ 20
ns
t
INH
t
INL
t
INO
t
IH
t
IS
PT CLOCK
INPUT
OUTPUT
AI03101
相關PDF資料
PDF描述
PSD813F1V Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813F2V-15 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD813F2V-20 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD813F2V-70 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD813F2V-90 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
相關代理商/技術參數
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