參數(shù)資料
型號(hào): PSD813F1A-90MT
廠商: 意法半導(dǎo)體
英文描述: Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
中文描述: Flash在系統(tǒng)可編程(ISP)的周邊8位MCU,5V的
文件頁數(shù): 36/110頁
文件大小: 1685K
代理商: PSD813F1A-90MT
PSD813F1
36/110
DECODE PLD (DPLD)
The DPLD, shown in Figure
16
, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals:
8 sector selects for the main Flash memory
(three product terms each)
4 sector selects for the EEPROM (three
product terms each)
I
I
I
1 internal SRAM select signal (two product
terms)
1 internal CSIOP (PSD configuration register)
select signal
1 JTAG select signal (enables JTAG on Port
C)
2 internal peripheral select signals (peripheral
I/O mode).
I
I
I
Figure 16. DPLD Logic Array
Note: 1. The address inputs are A19-A4 in 80C51XA mode.
(INPUTS)
(24)
(8)
(16)
(1)
PDN (APD OUTPUT)
I/O PORTS (PORT A,B,C)
(8)
PGR0 -PGR7
(8)
MCELLAB.FB [7:0] (FEEDBACKS)
MCELLBC.FB [7:0] (FEEDBACKS)
A[15:0]
(1)
(3)
(3)
PD[2:0] (ALE,CLKIN,CSI)
CNTRL[2:0] (READ/WRITE CONTROL SIGNALS)
(1)
(1)
RESET
RD_BSY
RS0
CSIOP
PSEL0
PSEL1
8 FLASH MEMORY
SECTOR SELECTS
SRAM SELECT
I/O DECODER
SELECT
PERIPHERAL I/O
MODE SELECT
EES 0
EES 1
EES 2
EES 3
FS0
FS7
3
3
3
3
3
3
3
3
3
3
3
3
2
JTAGSEL
AI09226
FS1
FS2
FS3
FS6
FS5
FS4
1
1
1
1
EEPROM
SELECTS
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PSD813F1A-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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PSD813F1A-90UT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD813F1AV-12JIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 3.3V
PSD813F1AV-12JT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 3.3V