參數(shù)資料
型號： PSD813F4V
英文描述： -200V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA597260 with Standard Packaging
中文描述： Flash在系統(tǒng)編程（ISP）外設的8位微控制器
文件頁數(shù)： 20/103頁
文件大?。?/td> 1185K
代理商： PSD813F4V
PSD81XFX, PSD83XF2, PSD85XF2
20/103
INSTRUCTIONS
An instruction consists of a sequence of specific
operations. Each received byte is sequentially de-
coded by the PSD8XXFX and not executed as a
standard WRITE operation. The instruction is exe-
cuted when the correct number of bytes are prop-
erly received and the time between two
consecutive bytes is shorter than the time-out pe-
riod. Some instructions are structured to include
READ operations after the initial WRITE opera-
tions.
The instruction must be followed exactly. Any in-
valid combination of instruction bytes or time-out
between two consecutive bytes while addressing
Flash memory resets the device logic into READ
Mode (Flash memory is read like a ROM device).
The PSD8XXFX supports the instructions summa-
rized in Table 8:
Flash memory:
I
Erase memory by chip or sector
I
Suspend or resume sector erase
I
Program a Byte
I
Reset to READ Mode
I
Read primary Flash Identifier value
I
Read Sector Protection Status
I
Bypass (on the PSD833F2, PSD834F2,
PSD853F2 and PSD854F2)
These instructions are detailed in Table 8. For ef-
ficient decoding of the instructions, the first two
bytes of an instruction are the coded cycles and
are followed by an instruction byte or confirmation
byte. The coded cycles consist of writing the data
AAh to address X555h during the first cycle and
data 55h to address XAAAh during the second cy-
cle. Address signals A15-A12 are Don’t Care dur-
ing the instruction WRITE cycles. However, the
appropriate
Sector
Select
CSBOOT0-CSBOOT3) must be selected.
The primary and secondary Flash memories have
the same instruction set (except for Read Primary
Flash Identifier). The Sector Select signals deter-
mine which Flash memory is to receive and exe-
cute the instruction. The primary Flash memory is
selected if any one of Sector Select (FS0-FS7) is
High, and the secondary Flash memory is selected
if any one of Sector Select (CSBOOT0-
CSBOOT3) is High.
Power-down Instruction and Power-up Mode
Power-up Mode.
The PSD8XXFX internal logic
is reset upon Power-up to the READ Mode. Sector
Select (FS0-FS7 and CSBOOT0-CSBOOT3)
(FS0-FS7
or
must be held Low, and Write Strobe (WR, CNTL0)
High, during Power-up for maximum security of
the data contents and to remove the possibility of
a byte being written on the first edge of Write
Strobe (WR, CNTL0). Any WRITE cycle initiation
is locked when V
CC
is below V
LKO
.
READ
Under typical conditions, the MCU may read the
primary Flash memory or the secondary Flash
memory using READ operations just as it would a
ROM or RAM device. Alternately, the MCU may
use READ operations to obtain status information
about a Program or Erase cycle that is currently in
progress. Lastly, the MCU may use instructions to
read special data from these memory blocks. The
following sections describe these READ functions.
Read Memory Contents.
Primary Flash memory
and secondary Flash memory are placed in the
READ Mode after Power-up, chip reset, or a Reset
Flash instruction (see Table 8). The MCU can read
the memory contents of the primary Flash memory
or the
secondary Flash memory by using READ
operations any time the READ operation is not
part of an instruction.
Read Primary Flash Identifier.
The
Flash memory identifier is read with an instruction
composed of 4 operations: 3 specific WRITE oper-
ations and a READ operation (see Table 8). Dur-
ing the READ operation, address bits A6, A1, and
A0 must be 0,0,1, respectively, and the appropri-
ate Sector Select (FS0-FS7) must be High. The
identifier for the PSD813F2/3/4/5 is E4h, and for
the PSD83xF2 or PSD85xF2 it is E7h.
Read Memory Sector Protection Status.
The
primary Flash memory Sector Protection Status is
read with an instruction composed of 4 operations:
3 specific WRITE operations and a READ opera-
tion (see Table 8). During the READ operation, ad-
dress bits A6, A1, and A0 must be 0,1,0,
respectively, while Sector Select (FS0-FS7 or
CSBOOT0-CSBOOT3) designates the Flash
memory sector whose protection has to be veri-
fied. The READ operation produces 01h if the
Flash memory sector is protected, or 00h if the
sector is not protected.
The sector protection status for all NVM blocks
(primary Flash memory or secondary Flash mem-
ory) can also be read by the MCU accessing the
Flash Protection registers in PSD I/O space. See
the section entitled “Flash Memory Sector Pro-
tect”, on page 25, for register definitions.
primary
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PSD813F4VA-15U 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD813F2VA-15U RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD813F5-12JI 制造商:WSI 功能描述:
PSD813F5-15JI 制造商:WSI 功能描述:
PSD813F5-15U 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
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