參數(shù)資料
型號: PSD813F4V
英文描述: -200V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA597260 with Standard Packaging
中文描述: Flash在系統(tǒng)編程(ISP)外設(shè)的8位微控制器
文件頁數(shù): 35/103頁
文件大?。?/td> 1185K
代理商: PSD813F4V
35/103
PSD81XFX, PSD83XF2, PSD85XF2
Product Term Allocator
The CPLD has a Product Term Allocator. The PS-
Dabel compiler uses the Product Term Allocator to
borrow and place product terms from one macro-
cell to another. The following list summarizes how
product terms are allocated:
I
McellAB0-McellAB7 all have three native
product terms and may borrow up to six more
I
McellBC0-McellBC3 all have four native product
terms and may borrow up to five more
I
McellBC4-McellBC7 all have four native product
terms and may borrow up to six more.
Each macrocell may only borrow product terms
from certain other macrocells. Product terms al-
ready in use by one macrocell are not available for
another macrocell.
If an equation requires more product terms than
are available to it, then “external” product terms
are required, which consume other Output Macro-
cells (OMC). If external product terms are used,
extra delay is added for the equation that required
the extra product terms.
This is called product term expansion. PSDsoft
Express performs this expansion as needed.
Loading and Reading the Output Macrocells
(OMC).
The Output Macrocells (OMC) block oc-
cupies a memory location in the MCU address
space, as defined by the CSIOP block (see the
section entitled “I/O PORTS”, on page 48). The
flip-flops in each of the 16 Output Macrocells
(OMC) can be loaded from the data bus by a MCU.
Loading the Output Macrocells (OMC) with data
from the MCU takes priority over internal func-
tions. As such, the preset, clear, and clock inputs
to the flip-flop can be overridden by the MCU. The
ability to load the flip-flops and read them back is
useful in such applications as loadable counters
and shift registers, mailboxes, and handshaking
protocols.
Data can be loaded to the Output Macrocells
(OMC) on the trailing edge of Write Strobe (WR,
CNTL0) (edge loading) or during the time that
Write Strobe (WR, CNTL0) is active (level load-
ing). The method of loading is specified in PSDsoft
Express Configuration.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD813F4VA-15J 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD813F2VA-15J RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD813F4VA-15U 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD813F2VA-15U RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD813F5-12JI 制造商:WSI 功能描述:
PSD813F5-15JI 制造商:WSI 功能描述:
PSD813F5-15U 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64