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參數(shù)資料
| 型號： | PSD813F5 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| 中文描述： | Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器 |
| 文件頁數(shù)： | 14/110頁 |
| 文件大小： | 1685K |
| 代理商： | PSD813F5 |
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PSD813F1
14/110
PSD ARCHITECTURAL OVERVIEW
PSD devices contain several major functional
blocks. Figure
5
shows the architecture of the PSD
device. The functions of each block are described
briefly in the following sections. Many of the blocks
perform multiple functions and are user config-
urable.
Memory
The PSD contains the following memories:
a 1 Mbit Flash memory
a secondary 256 Kbit EEPROM memory
a 16 Kbit SRAM
Each of the memory blocks is briefly discussed in
the following paragraphs. A more detailed discus-
sion can be found in the section entitled
MEMORY
BLOCKS, page 18
.
The 1 Mbit Flash memory is the main memory of
the PSD. It is divided into 8 equally-sized sectors
that are individually selectable.
The 256 Kbit EEPROM or Flash memory is divided
into 4 equally-sized sectors. Each sector is individ-
ually selectable.
The 16 Kbit SRAM is intended for use as a
scratchpad memory or as an extension to the mi-
crocontroller SRAM. If an external battery is con-
nected to the PSD
’
s V
STBY
pin, data will be
retained in the event of a power failure.
Each sector of memory can be located in a differ-
ent address space as defined by the user. The ac-
cess times for all memory types includes the
address latching and DPLD decoding time.
PLDs
The device contains two PLD blocks, each opti-
mized for a different function, as shown in Table
2
.
The functional partitioning of the PLDs reduces
power consumption, optimizes cost/performance,
and eases design entry.
The Decode PLD (DPLD) is used to decode ad-
dresses and generate chip selects for the PSD in-
ternal memory and registers. The CPLD can
implement user-defined logic functions. The DPLD
has combinatorial outputs. The CPLD has 16 Out-
put macrocells and 3 combinatorial outputs. The
PSD also has 24 Input macrocells that can be con-
figured as inputs to the PLDs. The PLDs receive
their inputs from the PLD Input Bus and are differ-
entiated by their output destinations, number of
Product Terms, and macrocells.
I
I
I
The PLDs consume minimal power by using Zero-
Power design techniques. The speed and power
consumption of the PLD is controlled by the Turbo
Bit (ZPSD only) in the PMMR0 register and other
bits in the PMMR2 registers. These registers are
set by the microcontroller at runtime. There is a
slight penalty to PLD propagation time when in-
voking the ZPSD features.
I/O Ports
The PSD has 27 I/O pins divided among four ports
(Port A, B, C, and D). Each I/O pin can be individ-
ually configured for different functions. Ports A, B,
C and D can be configured as standard MCU I/O
ports, PLD I/O, or latched address outputs for mi-
crocontrollers using multiplexed address/data
busses.
The JTAG pins can be enabled on Port C for In-
System Programming (ISP).
Ports A and B can also be configured as a data
port for a n on-multiplexed bus or multiplexed Ad-
dress/Data buses for certain types of 16-bit micro-
controllers.
Microcontroller Bus Interface
The PSD easily interfaces with most 8-bit micro-
controllers that have either multiplexed or non-
multiplexed address/data busses. The device is
configured to respond to the microcontroller
’
s con-
trol signals, which are also used as inputs to the
PLDs. Where there is a requirement to use a 16-
bit data bus to interface to a 16-bit microcontroller,
two PSDs must be used. For examples, please
see the section entitled
MCU Bus Interface
Examples, page 47
.
Table 2. PLD I/O
Name
Inputs
Outputs
Product
Terms
Decode PLD (DPLD)
73
17
42
Complex PLD (CPLD)
73
19
140
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相關(guān)代理商/技術(shù)參數(shù) |
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| PSD813F5-12JI | 制造商:WSI 功能描述: |
| PSD813F5-15JI | 制造商:WSI 功能描述: |
| PSD813F5-15U | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64 |
| PSD813F5-90J | 制造商:WSI 功能描述: |
| PSD813F5-90U | 制造商:WSI 功能描述: |
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