參數(shù)資料
型號(hào): PSD813F5
廠商: 意法半導(dǎo)體
英文描述: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù): 68/110頁
文件大?。?/td> 1685K
代理商: PSD813F5
PSD813F1
68/110
Input Control Signals
The PSD provides the option to turn off the input
control signals (CNTL0, CNTL1, CNTL2, ALE, and
DBE) to the PLD to save AC power consumption.
These control signals are inputs to the PLD AND
array.
During Power Down Mode, or, if any of them are
not being used as part of the PLD logic equation,
these control signals should be disabled to save
AC power. They will be disconnected from the
PLD AND array by setting bits 2, 3, 4, 5, and 6 to
a
1
in the PMMR2.
Table 32. APD Counter Operation
APD Enable Bit
ALE PD Polarity
ALE Level
APD Counter
0
X
X
Not Counting
1
X
Pulsing
Not Counting
1
1
1
Counting (Generates PDN after 15 Clocks)
1
0
0
Counting (Generates PDN after 15 Clocks)
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