參數(shù)資料
型號(hào): Q67121C452
英文描述: IC-SM-8-BIT CPU-12MHZ
中文描述: 集成電路釤8位CPU - 12MHz的
文件頁(yè)數(shù): 64/121頁(yè)
文件大小: 1000K
代理商: Q67121C452
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Semiconductor Group
6-30
On-Chip Peripheral Components
C501
6.3.1 Multiprocessor Communications
Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data
bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed
such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This
feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor systems
is as follows.
When the master processor wants to transmit a block of data to one of several slaves, it first sends
out an address byte which identifies the target slave. An address byte differs from a data byte in
that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted
by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine
the received byte and see if it is beeing addressed. The addressed slave will clear its SM2 bit and
prepare to receive the data bytes that will be coming. The slaves that weren’t being addressed leave
their SM2s set and go on about their business, ignoring the incoming data bytes.
SM2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit. In a
mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is
received.
6.3.2 Serial Port Registers
The serial port control and status register is the special function register SCON. This register
contains not only the mode selection bits, but also the 9th data bit for transmit and receive TB8 and
RB8), and the serial port interrupt bits (TI and RI).
SBUF is the receive and transmit buffer of serial interface. Writing to SBUF loads the transmit
register and initiates transmission. Reading out SBUF accesses a physically separate receive
register.
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