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參數(shù)資料
| 型號(hào)： | Q67121C452 |
| 英文描述： | IC-SM-8-BIT CPU-12MHZ |
| 中文描述： | 集成電路釤8位CPU - 12MHz的 |
| 文件頁數(shù)： | 92/121頁 |
| 文件大?。?/td> | 1000K |
| 代理商： | Q67121C452 |
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Semiconductor Group
8-3
Power Saving Modes
C501
8.3
Power Down Mode
In the power down mode, the on-chip oscillator is stopped. Therefore all functions are stopped; only
the contents of the on-chip RAM and the SFR’s are maintained. The port pins controlled by their port
latches output the values that are held by their SFR’s. The port pins which serve the alternate output
functions show the values they had at the end of the last cycle of the instruction which initiated the
power-down mode. ALE and PSEN hold at logic low level (see
table 9-1
).
The power-down mode is entered by setting the flag bit PDE (PCON.1).
Note:
PCON is not a bit-addressable register, so the above mentioned sequence for entering the power
down mode is obtained by a byte-handling instruction, as shown in the following example:
ORL
PCON,#00000010B
;Set bit PDE
The instruction that sets bit PDE is the last instruction executed before going into power down
mode. The only exit from power down mode is a hardware reset. Reset will redefine all SFR’s, but
will not change the contents of the internal RAM.
In the power down mode of operation,
V
CC
can be reduced to minimize power consumption. It must
be ensured, however, that
V
CC
is not reduced before the power down mode is invoked, and that
V
CC
is restored to its normal operating level, before the power down mode is terminated. The reset signal
that terminates the power down mode also restarts the oscillator.
The
reset
should
not
be
activated
before
V
CC
is
restored
to
its
normal
operating level and must be held active long enough to allow
the oscillator to restart and stabilize (similar to power-on reset).
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