參數(shù)資料
型號(hào)： QL1P100-8PUN86M
廠商： QUICKLOGIC CORP
元件分類： FPGA
英文描述： FPGA, 640 CLBS, 100000 GATES, PBGA86
封裝： 6 X 6 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, TFBGA-86
文件頁(yè)數(shù)： 3/44頁(yè)
文件大?。?/td> 1101K
代理商： QL1P100-8PUN86M
2010 QuickLogic Corporation
QuickLogic PolarPro Device Data Sheet — 86-Pin TFBGA QL1P100 Rev. G
11
86-Pin TFBGA QL1P100 Clock Network Architecture
Clock Network Architecture
The PolarPro clock network architecture consists of a 2-level H-tree network as shown in Figure 9. The first
level of each clock tree (high-lighted in red) spans from the clock input pad to the global clock network and to
the center of each quadrant of the chip. The second level (high-lighted in blue) spans from the quadrant clock
network to every logic cell inside that quadrant. There are five global clocks in the global clock network, and
five quadrant clocks in each quadrant clock network. All global clocks drive the quadrant clock network inputs.
The quadrant clocks output to clock inversion muxes, which pass either the original input clock or an inverted
version of the input clock to the logic cells in that quadrant. The global clocks can drive RAM block clock inputs
and reset, set, enable, and clock inputs to I/O registers. Furthermore, the quadrant clock outputs can be routed
to all logic cell inputs.
Figure 9: PolarPro Clock Architecture
Of the five global clock networks, four can be either driven directly by clock pads, Configurable Clock Manager
(CCM) outputs, or internally generated signals. These four global clocks go through 3-input global clock muxes
located in the middle of the die. See Figure 10 for a diagram of a 3-input global clock mux. The fifth is a
dedicated global clock network that goes directly to the quadrant clock network and is used as a dedicated fast
clock.
Quadrant
Clock
Network
Global Clock
Network
x4
Inversion
Mux
Quadrant
Clock
Network
Quadrant
Clock
Network
Quadrant
Clock
Network
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