QL5064 QuickPCI Data Sheet
Figure 9: QuickWorks Tool Suite
15.0 JTAG Support
JTAG pins support IEEE standard 1149.1a to provide boundary scan capability for QL5064 devices.
Six pins are dedicated to JTAG and programming functions on each QL5064 device, and are unavailable
for general design input and output signals. TDI, TDO, TCK, TMS, and TRSTB are JTAG pins. A sixth
pin, STM, is used only for programming.
16.0 Development Tool Support
Software support for the QL5064 device is available through the QuickWorks development package.
This turnkey PC-based QuickWorks package, shown in Figure 9, provides a complete ESP software
solution with design entry, logic synthesis, place and route, and simulation. QuickWorks includes VHDL,
Verilog, schematic, and mixed-mode entry with fast and efficient logic synthesis provided by the
integrated Synplicity Synplify Lite tool, specially tuned to take advantage of the QL5064 architecture.
QuickWorks also provides functional and timing simulation for guaranteed timing and source-level
debugging.
The UNIX-based QuickTools‘ and PC-based QuickWorks-Lite packages are a subset of QuickWorks and
provide a solution for designers who use schematic-only design flow third-party tools for design entry,
synthesis, or simulation. QuickTools and QuickWorks-Lite read EDIF netlists and provide support for all
QuickLogic devices. QuickTools and QuickWorks-Lite also support a wide range of third-party modeling
and simulation tools. In addition, the PC-based package combines all the features of QuickWorks-Lite
with the SCS schematic capture environment, providing a low-cost design entry and compilation
solution.
Schematic
Turbo Writer
HDL Editor
Third Party
Design
Entry
& Synthesis
Third Party
Simulation
VHDL/
Verilog
SCS Schematic
Tools
Silos
&
Simulators
Quick
Tools
/Quick
Chip
:
Optimize, Place, &
Route
Mixed-Mode Design
Synplify-Lite
HDL
Synthesis
Quick
Works
Design Software